ch7013b ETC-unknow, ch7013b Datasheet
ch7013b
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ch7013b Summary of contents
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... Rev. 1.2, 9/1/2004 Digital Encoder 2. G ENERAL Chrontel’s CH7013B digital encoder is a stand- alone integrated circuit providing a robust solution for TV output. It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts it directly into the NTSC or PAL TV format ...
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... CHRONTEL ESCRIPTIONS 3.1 Package Diagram D[3] 1 D[4] 2 D[5] 3 D[6] 4 DVDD 5 D[7] 6 D[8] 7 DGND 8 9 D[9] 10 D[10] D[11 Figure 2: 48-PIN LQFP (7mm x 7mm) 2 CHRONTEL CH7013B 201-0000-069 CH7013B 36 XO/FIN AVDD 33 DVDD 32 ADDR 31 DGND 30 CLOCK 29 DATA 28 VDD 27 RSET 26 GND 25 NC Rev. 1.2, 9/1/2004 ...
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... Digital Input Port. Pixel Clock Output The CH7013B, operating in master mode, provides a pixel data clocking signal to the VGA controller. This pin provides the pixel clock output signal (adjustable 3X) to the VGA controller (see the section on Digital Video Interface and Registers and Programming for more details) ...
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... Please refer to AN47 for details. Analog ground These pins provide the ground reference for the analog section of the CH7013B, and MUST be connected to the system ground, to prevent latchup. Refer to the Application Information section for information on proper supply de-coupling. ...
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... Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7013B. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first value of the (Total Pixels/Line x Total Lines/Frame) column of the description) ...
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... Y0[7] R1[3] R2[4] R3[4] Y0[6] R1[2] R2[3] R3[3] Y0[5] R1[1] R2[2] R3[2] Y0[4] R1[0] R2[1] R3[1] Y0[3] G1[5] R2[0] R3[0] Y0[2] G1[4] G2[4] G3[4] Y0[1] G1[3] G2[3] G3[3] Y0[0] G1[2] G2[2] G3[2] Cb0[7] G1[1] G2[1] G3[1] Cb0[6] G1[0] G2[0] G3[0] Cb0[5] B1[4] B2[4] B3[4] Cb0[4] B1[3] B2[3] B3[3] Cb0[3] B1[2] B2[2] B3[2] Cb0[2] B1[1] B2[1] B3[1] Cb0[1] B1[0] B2[0] B3[0] Cb0[0] CH7013B t PH1 SP t HP1 YCrCb (16-bit Y1[7] Y2[7] Y3[7] Y1[6] Y2[6] Y3[6] Y1[5] Y2[5] Y3[5] Y1[4] Y2[4] Y3[4] Y1[3] Y2[3] Y3[3] Y1[2] Y2[2] Y3[2] Y1[1] Y2[1] Y3[1] Y1[0] Y2[0] Y3[0] Cr0[7] Cb2[7] Cr2[7] Cr0[6] Cb2[6] Cr2[6] Cr0[5] Cb2[5] Cr2[5] Cr0[4] Cb2[4] Cr2[4] Cr0[3] Cb2[3] Cr2[3] Cr0[2] Cb2[2] Cr2[2] Cr0[1] Cb2[1] Cr2[1] Cr0[0] Cb2[0] Cr2[0] 201-0000-069 Rev ...
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... Y2[2] S[1] Y0[1] Y1[1] Y2[1] S[0] Y0[0] Y1[0] Y2[0] 0 Cb0[7] Cr0[7] Cb2[7] 0 Cb0[6] Cr0[6] Cb2[6] 0 Cb0[5] Cr0[5] Cb2[5] 0 Cb0[4] Cr0[4] Cb2[4] 0 Cb0[3] Cr0[3] Cb2[3] 0 Cb0[2] Cr0[2] Cb2[2] 0 Cb0[1] Cr0[1] Cb2[1] 0 Cb0[0] Cr0[0] Cb2[0] CH7013B Y3[7] Y4[7] Y5[7] Y3[6] Y4[6] Y5[6] Y3[5] Y4[5] Y5[5] Y3[4] Y4[4] Y5[4] Y3[3] Y4[3] Y5[3] Y3[2] Y4[2] Y5[2] Y3[1] Y4[1] Y5[1] Y3[0] Y4[0] Y5[0] Cr2[7] Cb4[7] Cr4[7] Cr2[6] Cb4[6] Cr4[6] Cr2[5] Cb4[5] Cr4[5] Cr2[4] Cb4[4] Cr4[4] Cr2[3] Cb4[3] ...
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... P2 t SP2 P0a P0b 7 RGB 5-6-5 P0b P1a P1b P0a R0[4] G1[2] R1[4] G0[2] R0[3] G1[1] R1[3] G0[1] R0[2] G1[0] R1[2] G0[0] R0[1] B1[4] R1[1] B0[4] R0[0] B1[3] R1[0] B0[3] G0[5] B1[2] G1[5] B0[2] G0[4] B1[1] G1[4] B0[1] G0[3] B1[0] G1[3] B0[0] 4 12-bit RGB (12-12) P0b P1a P1b P0a R0[7] G1[3] R1[7] G0[4] R0[6] G1[2] R1[6] G0[3] R0[5] G1[1] R1[5] G0[2] R0[4] G1[0] R1[4] B0[7] R0[3] B1[7] R1[3] B0[6] R0[2] B1[6] R1[2] B0[5] R0[1] B1[5] R1[1] B0[4] R0[0] B1[4] R1[0] B0[3] G0[7] B1[3] G1[7] G0[0] G0[6] B1[2] G1[6] B0[2] G0[5] B1[1] G1[5] B0[1] G0[4] B1[0] G1[4] B0[0] CH7013B t PH2 t HP2 t t SP2 HP2 t t SP2 HP2 P1a P1b P2a P2b 8 RGB 5-5-5 P0b P1a P1b x G1[2] x R0[4] G1[1] R1[4] R0[3] G1[0] R1[3] R0[2] B1[4] R1[2] R0[1] B1[3] R1[1] R0[0] B1[2] R1[0] G0[4] B1[1] G1[4] G0[3] B1[0] G1[3] 5 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 201-0000-069 Rev. 1.2, 9/1/2004 ...
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... Rev. 1.2, 9/1/2004 2 16-bit RGB (16-8) P0b P1a P1b A0[7] G1[7] A1[7] A0[6] G1[6] A1[6] A0[5] G1[5] A1[5] A0[4] G1[4] A1[4] A0[3] G1[3] A1[3] A0[2] G1[2] A1[2] A0[1] G1[1] A1[1] A0[0] G1[0] A1[0] R0[7] B1[7] R1[7] R0[6] B1[6] R1[6] R0[5] B1[5] R1[5] R0[4] B1[4] R1[4] R0[3] B1[3] R1[3] R0[2] B1[2] R1[2] R0[1] B0[1] R1[1] R0[0] B0[0] R1[0] 9 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7013B P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 9 ...
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... S[ SP3 P0a P0b 6 RGB 8-bit P0b P0c P1a P1b G0[7] R0[7] B1[7] G1[7] G0[6] R0[6] B1[6] G1[6] G0[5] R0[5] B1[5] G1[5] G0[4] R0[4] B1[4] G1[4] G0[3] R0[3] B1[3] G1[3] G0[2] R0[2] B1[2] G1[2] G0[1] R0[1] B1[1] G1[1] G0[0] R0[0] B1[0] G1[0] CH7013B P2a P2b P3a P3b Cb2[7] Y2[7] Cr2[7] Y3[7] Cb2[6] Y2[6] Cr2[6] Y3[6] Cb2[5] Y2[5] Cr2[5] Y3[5] Cb2[4] Y2[4] Cr2[4] Y3[4] Cb2[3] Y2[3] Cr2[3] Y3[3] Cb2[2] Y2[2] Cr2[2] Y3[2] Cb2[1] Y2[1] Cr2[1] Y3[1] Cb2[0] Y2[0] Cr2[0] Y3[0] t PH3 t HP3 P0c P1a P1b P1c P1c P2a P2b ...
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... TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7013B can render a superior TV image without the added cost of a full frame buffer memory – normally used to implement features such as scaling and full synchronization ...
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... Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer. In addition to the above mode table, the CH7013B also support interlaced input modes, both in CCIR 656 and proprietary formats (see Display Mode Register section.) ...
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... Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the serial port, the CH7013B may be placed in either Normal state, or any of the four power managed states, as listed below (see “ Power Management Register” under the Register Descriptions section for programming information). To support power management sensing function (see “ ...
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... CHRONTEL 4.4 Luminance and Chrominance Filter Options The CH7013B contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S- Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and chrominance video bandwidth output is shown in Table 13 ...
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... YSVdB -18 <i> (YSVdB ) n -24 -30 -36 - Figure 7: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0) 201-0000-069 Rev. 1.2, 9/1/2004 n CH7013B ...
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... CHRONTEL Luminance and Chrominance Filter Options (continued -12 < > i UVfirdB -18 n <i> (UVfirdB ) n -24 -30 -36 - Figure 8: Chrominance Frequency Response n CH7013B 201-0000-069 Rev. 1.2, 9/1/2004 ...
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... Table 14 and shown in Figure 9 . (See Figures 12 through 17 for illustrations of composite and S-Video output waveforms.) 4.5.1 CCIR624-3 Compliance The CH7013B is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance: • The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or pseudo-master modes, not in slave mode when the graphics device generates these frequencies. • ...
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... CH7013B 271 272 273 274 275 268 268 269 269 270 270 271 271 ...
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... FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 317 4 3 ° ° ° ° ° ° CH7013B 318 319 320 321 322 323 318 319 320 321 322 323 6 ...
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... Figure 12: NTSC Y (Luminance) Output Waveform (DACG = 0) Color/Level mA V White 26.75 1.003 Yellow 24.62 0.923 Cyan 21.11 0.792 Green 18.98 0.712 Magenta 15.62 0.586 Red 13.49 0.506 Blue 10.14 0.380 Blank/ Black 8.00 0.300 Sync 0.00 0.000 Figure 13: PAL Y (Luminance) Video Output Waveform (DACG = 1) 20 Color bars: Color bars: 201-0000-069 CH7013B Rev. 1.2, 9/1/2004 ...
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... Cyan/Red 27.51 1.032 Green/Magenta 26.68 1.000 Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 15: PAL C (Chrominance) Video Output Waveform (DACG = 1) 201-0000-069 Rev. 1.2, 9/1/2004 Color bars: (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7013B 21 ...
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... Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 17: Composite PAL Video Output Waveform (DACG = 1) 22 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7013B 201-0000-069 Rev. 1.2, 9/1/2004 ...
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... The CH7013B is a fully programmable device, providing for full functional control through a set of registers accessed from the serial port. The CH7013B contains a total of 37 registers, which are listed in Table 15 and described in detail under Register Descriptions . Detailed descriptions of operating modes and their effects are con- tained in the previous section, Functional Description ...
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... CIV5 CIV4 CIV3 VID5 VID4 VID3 TS1 TS0 RSA MS2 MS1 MSO YLM5 YLM4 YLM3 CLM5 CLM4 CLM3 AR5 AR4 AR3 CH7013B ) Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 FY0 FT1 FT0 YSV1 YSV0 YCV IDF2 IDF1 IDF0 XCM0 PCM1 PCM0 SAV2 ...
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... R/W R/W Type Default: This register provides programmable control of the CH7013B display mode, including input resolution (IR[2:0]), output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the table below (default is 640x480 input, NTSC output, 7/8’s scaling). Table 17. Display Modes VOS SR Mode ...
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... Settings for Chroma Channel 00 Minimal Flicker Filtering 01 Slight Flicker Filtering 10 Maximum Flicker Filtering 11 Enable Chroma DotCrawl Reduction NTSC PAL FC1 FC0 FY1 R/W R/W R CH7013B 11 NTSC-J Symbol: FFR Address: 01h Bits FY0 FT1 FT0 R/W R/W R 201-0000-069 Rev. 1.2, 9/1/2004 ...
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... The default setting of 0 uses a four line flicker filter. 201-0000-069 Rev. 1.2, 9/1/2004 Reserved Reserved Reserved R/W R/W R CBW1 CBW0 YPEAK R/W R/W R CH7013B Symbol: Address: 02h Bits Reserved Reserved Reserved R/W R/W R Symbol: VBW Address: 03h Bits YSV1 YSV0 YCV R/W R/W ...
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... Default: The setting of the clock mode bits determines the clocking mechanism used in the CH7013B. The clock modes are shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the XCLK input clock. Note: For what was formerly defined as the master mode, the user must now externally connect the P-OUT clock to the XCLK input pin ...
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... SAV5 SAV4 SAV3 R/W R/W R Reserved Reserved Reserved R/W R/W R CH7013B Symbol: SAV Address: 07h Bits SAV2 SAV1 SAV0 R/W R/W R Symbol: PO Address: 08h Bits SAV8 HP8 VP8 R/W R/W R ...
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... BL4 BL3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7013B Symbol: BLR Address: 09h Bits BL2 BL1 BL0 R/W R/W R Symbol: HPR Address: 0Ah Bits HP2 HP1 HP0 R/W R/W R Symbol: VPR Address: 0Bh ...
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... VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low, and a value of one means the vertical sync is active high. • SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7013B. A value of one means that H and V sync are output from the CH7013B. ...
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... Default: This register provides control of the contrast enhancement feature of the CH7013B, according to the table below setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of 011 ...
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... The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7013B is operating in master or pseudo-master clock mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value ...
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... The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase detector, when the CH7013B is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master and pseudo- ...
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... FSCI[3:0] When the CH7013B is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21h should be set to “0”, and the CFRB bit in register 06h should be set to “1”. ...
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... Programming Note: Bit 1 and bit 3 of this register must be programmed PAL-Nc (Argentina) “Normal Dot Crawl” 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 569,807,942 867,513,766 PLLCPI PLLCAP PLLS R/W R/W R CH7013B Symbol: PLLC Address: 20h Bits Reserved PLLVA Reserved R/W R/W R 201-0000-069 Rev. 1.2, 9/1/2004 ...
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... See descriptions in the next section. 201-0000-069 Rev. 1.2, 9/1/2004 PLLCAP Value Reserved CIV25 CIV24 R R CH7013B Symbol: CIVC Address: 21h Bits CIVH1 CIVH0 ACIV R/W R/W R ...
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... Default: This read-only register contains a 8-bit value indicating the identification number assigned to this version of the CH7013B. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming. Address Register ...
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... S-Video & composite outputs) DVDD (3.3V) current RSET = 300 : and NTSC CCIR601 operation. 201-0000-069 Rev. 1.2, 9/1/2004 Min - 0.5 1 GND - 0 Min 3.15 3.15 3. 3.3V, AVDD = 3.3V, DVDD = 3.3V) DD Min CH7013B Typ Max Units 7.0 V VDD + 0.5 V Indefinite Sec 85 qC 150 qC 150 qC 220 qC Typ Max Units 3.3 3.45 V 3.3 3. ...
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... CHRONTEL Table 34. CH7013B Supply Current Characteristics (AVDD = 3.3V, VDD = 3.3V, DVDD = 3.3V) Description Normal Operation IDD1 IDD2 IDD3 Normal Operation S-Video only IDD1 IDD2 IDD3 Normal Operation, composite only IDD1 IDD2 IDD3 Full Power Down Total of DVDD, AVDD, & VDD supply currents IDD Notes ...
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... Pixel Clock Duty Cycle (t t Pixel Clock Period P3 t Pixel Clock High Time PH3 tdc3 Pixel Clock Duty Cycle (t 201-0000-069 Rev. 1.2, 9/1/2004 Min PH1 PH2 PH3 P3 CH7013B Typ Max Unit ...
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... D[11:0], H, & V rise/fall time w/15pF load Notes: 1. DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. 2. VREF: I/O Reference voltage. In general cases, VREF = DVDDV/ VGA Line t5 DVDDV (2) = 1. (D[11:0], H, & (D[11:0], H, & V) CH7013B P0a P1a P2a Min Typ Max Unit ...
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... DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. 2. VREF: I/O Reference voltage. In general cases, VREF = DVDDV/2. 201-0000-069 Rev. 1.2, 9/1/2004 t7 64 PIXELS 1 VGA Line t5 t2 DVDDV (2) = 1.65 V (2) ) (2) ) (2) ) (2) ) CH7013B P0a P0b P1a P1b P2a P2b t5 Min Typ Max Unit (1) (1) -0.2 DVDDV +0.2 -0.2 ...
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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. Dimension B does not include allowable mold protrusions up to 0.25 mm per side SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 CH7013B LEAD CO-PLANARITY E .004 “ 0.45 0.09 0q 1.00 0.75 0.20 7q 201-0000-069 Rev. 1.2, 9/1/2004 ...
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... CHRONTEL EVISION ISTORY Rev. # Date Section 1.0 5/25/04 All 1.1 7/12/04 6 1.2 9/1/04 5 & 6 201-0000-069 Rev. 1.2, 9/1/2004 Description First official release of CH7013B datasheet, rev. 1.0 Power down currents updated Supported modes updated. Current consumption updated CH7013B 45 ...
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... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part number CH7013B-D CH7013B-D-TR CH7013B-DF CH7013B-DF-TR ”2004 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 46 Disclaimer ORDERING INFORMATION ...