ch7013b ETC-unknow, ch7013b Datasheet - Page 33

• Manufacturer Part Number: ch7013b
• Description: Digital Pc To Tv Encoder
• Manufacturer: ETC-unknow

CHRONTEL
PLL Overflow Register
The PLL Overflow Register contains the MSB bits for the ‘M’ and ‘N’ vlaues, which will be described in the PLL-
M and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7013B is operating in master or pseudo-master clock mode. In slave mode, an
external pixel clock is used instead of the frequency reference, and the division factor is determined by the
XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
PLL N Value Register
201-0000-069
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Figure 18: Luma Transfer Function at different contrast enhancement settings
7
Reserved
R/W
7
M7
R/W
0
7
N7
R/W
1
0
Rev. 1.2, 9/1/2004
6
Reserved
R/W
1
6
M6
R/W
1
6
N6
R/W
0
256
224
192
160
128
96
64
32
0
0
32
5
Reserved
0
5
M5
R/W
0
5
N5
R/W
0
R/W
64
96
4
Reserved
R/W
0
4
M4
R/W
0
4
N4
R/W
0
128
160
3
Reserved
R/W
0
3
M3
R/W
0
3
N3
R/W
0
192
224 256
2
N9
0
2
M2
0
2
N2
0
R/W
R/W
R/W
Symbol: MNE
Address: 13h
Bits: 5
Symbol: PLLM
Address: 14h
Bits: 8
Symbol: PLLN
Address: 15h
Bits: 8
1
N8
R/W
0
1
M1
R/W
0
1
N1
R/W
0
CH7013B
0
M8
R/W
0
0
M0
R/W
1
0
N0
R/W
0
33