ch7013b ETC-unknow, ch7013b Datasheet - Page 36

• Manufacturer Part Number: ch7013b
• Description: Digital Pc To Tv Encoder
• Manufacturer: ETC-unknow

When the CH7013 is operating in the slave clock mode, the ACIV bit in register 21h should be set to “1” and the
CFRB bit in register 06h should be set to “0”.
PLL Control Register
The following PLL and memory controls are available through the PLL control register:
PLLVA
PLLS
PLLCAP
PLLCPI
CHRONTEL
*Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0"
36
Table 29. FSCI Values (625-Line Modes)
Bit:
Symbol:
Type:
Default:
*
Mode
Programming Note: Bit 1 and bit 3 of this register must be programmed to 0.
13
14
15
19
20
21
25
27
0
1
4
5
8
9
& ACIV = "0".
Reserved
R/W
PLLS controls the number of stages used in the PLL and must be changed to 0. When PLLS is set
PLLCPI controls the charge pump current of the PLL. The default value should be used.
PLLVA must be set to 0 when the phase-locked loop analog supply is 3.3 volts. The default value
of this bit should be overwritten and set to 0.
to 0, five stages are used in the PLL.The default value of this bit should be overwritten and set to 0.
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.
Mode is shown below
7
0
“Normal Dot Crawl”
Reserved
R/W
1,073,747,879
488,262,757*
806,021,060
644,816,848
601,829,058
485,346,014
677,057,690
537,347,373
806,021,060
644,816,848
537,347,373
645,499,916
528,951,320
705,268,427
6
0
PAL
PLLCPI
R/W
5
0
PLLCAP
R/W
4
0
PLLS
R/W
“Normal Dot Crawl”
PAL-Nc (Argentina)
1*
3
651,209,077
520,967,262
392,125,896
547,015,625
434,139,385
651,209,077
520,967,262
434,139,385
521,519,134
427,355,957
394,482,422
569,807,942
867,513,766
486,236,111
Reserved
R/W
201-0000-069
2
0
Symbol: PLLC
Address: 20h
Bits: 6
PLLVA
R/W
1*
1
Rev. 1.2, 9/1/2004
CH7013B
Reserved
R/W
0
0