MP7226KP EXAR [Exar Corporation], MP7226KP Datasheet - Page 8

• Manufacturer Part Number: MP7226KP
• Description: BiCMOS Fixed, Quad, Voltage Output, Single or Dual Supply 8-Bit Digital-to-Analog Converter
• Manufacturer: EXAR [Exar Corporation]

AGND
the power dissipation of the package should not exceed the
maximum limit.
Digital Inputs
face compatibility and can also be driven directly with 5V CMOS
logic inputs. The digital inputs are ESD protected to a rating of
2000 volts.
Digital Interface Logic
buses without additional interface circuitry.
Table 1. shows the control logic truth table and operation for
WR, A1, A0. The address lines A0, and A1 determine which
DAC will accept the input data. The WR input determines
whether the selected DAC is transparent (output follows the in-
put), latched, or no operation. The WR input will also inhibit
power on reset of the DAC latches to 0, if its initial state = 0 after 5
signal is low, the input latch of the selected DAC is transparent,
and the DAC’s output corresponds to the value present on the
data bus. On some data buses, data is not always valid for the
entire period that the WR signal is low and can cause unwanted
data at the output. Ensuring that the write pulse (WR) conforms
to the data hold time, (t4) spec will prevent this problem.
MP7226
V
s of power.
V
DD
The amplifiers outputs may be shorted to ground. However,
All of the digital inputs to this DAC maintain TTL level inter-
The MP7226 allows direct interface to most microprocessor
Figure 3. shows the input control logic circuit diagram and
Figure 4. shows the write cycle timing diagram. When the WR
IN
Figure 2. Simplified Output Buffer Amplifiers
Rev. 2.00
Output
V
SS
8
WR
A0
A1
Address
NOTE: When the WR signal is low, the input latch of the se-
lected DAC is transparent and any invalid data at this time will
cause erroneous output.
Data
WR
Figure 4. Write Cycle Timing Diagram
WR
H
L
L
L
L
Figure 3. Input Control Logic
Decoder
A1
1 of 4
X
H
H
L
L
L
Table 1. Truth Table
t
A0
AS
H
H
X
L
L
L
No Operation;
Device Not Selected
DAC 1 Transparent
DAC 1 Latched
DAC 2 Transparent
DAC 3 Transparent
DAC 4 Transparent
t
V
WR
V
INH
Operation
INL
t
DS
To DAC1 Latch Enable
To DAC2 Latch Enable
To DAC3 Latch Enable
To DAC4 Latch Enable
t
AH
t
DH
5 V
0 V
5 V
0 V
5 V
0 V