kac-9628 ETC-unknow, kac-9628 Datasheet - Page 11

• Manufacturer Part Number: kac-9628
• Description: Kodak Kac-9628 Cmos Image Sensor 648 H X 488 V High Dynamic Range 30 Fps Color Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
1.0
1.1
The KAC-9628 contains a CMOS active pixel array consisting of
488 rows by 648 columns. This active region is surrounded by 8
columns and 8 rows of optically shielded (black) pixels as shown
in Figure7.
The color filters are Bayer pattern coded starting at row 8 and
column 8. (rows 0 to 7 & columns 0 to 7 are black). The color
coding is green, red, green, red until the end of row 8, then blue,
green, blue, green until the end or row 9 and so on (see Figure
7).
At the beginning of a given integration time the on-board timing
and control circuit will reset every pixel in the array one row at a
time as shown in Figure 8
Note that all pixels in the same row are simultaneously reset, but
not all pixels in the array
At the end of the integration time, the timing and control circuit
will address each row and simultaneously transfer the integrated
value of the pixel to a correlated double sampling circuit and
then to a shift register as shown in Figure 8.
Once the correlated double sampled data has been loaded into
the shift register, the timing and control circuit will shift them out
one pixel at a time starting with column “a”.
The pixel data is then fed into an analog video amplifier, where a
user programmed gain is applied, then to the color amplifiers
(red, green, blue), where each color gain can be individually
adjusted (see Figure ).
www.kodak.com/go/imagers 585-722-4385
8 columns, 8 rows
color (Bayer pattern) active pixels
black pixels
Light Capture and Conversion
OVERVIEW
Figure 7: CMOS APS region of the KAC-9628
648 columns, 488 rows
Analog Data Out
Figure 8. Sensor Addressing Scheme
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
a b c d e f g h i
CDS/Shift Register
8 columns, 8 rows
black pixels
j
k l m n o p q r
11
After gain and color gain adjustment the analog value of each
pixel is converted to 12 bit digital data as shown in Figure .
Analog Signals Conditioning & Conversion to Digital
The digital pixel data is further processed to:
• remove defects due to bad pixels,
• compensate black level, before being framed and presented
1.2
The programming, control and status monitoring of the KAC-
9628 is achieved through a two wire I
In addition, a slave address pin is provided (see Figure 10).
Additional control and status pins: snapshot and external event
synchronization are provided allowing the latency of the serial
control port to be bypassed during single frame capture. An
interrupt request pin is also available allowing complex snapshot
operations to be controlled via an external micro-processor (see
Figure 11).
Analog pixel values
on the digital output port. (see Figure 9).
Figure 11. Snapshot & External Event Trigger Signals
Register Bank
Video
AMP
Program and Control Interfaces
Figure 10. Control Interface to the KAC-9628.
0-15dB
Figure 9. Digital Pixel Processing.
Generator
0-14dB
G
R
B
0-14dB
Timing
0-14dB
I
2
C Compatible
Serial I/F
MUX
Email:[e-mail]
2
C compatible serial bus.
Digital pixel data
extsyn
snapshot
12 Bit A/D
sadr
sda
sclk
vsync
do[11:0]
pclk
hsync