kac-9638 ETC-unknow, kac-9638 Datasheet - Page 21

• Manufacturer Part Number: kac-9638
• Description: Kodak Kac-9638 Cmos Image Sensor
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
11.0 DIGITAL VIDEO PORT
The captured image is placed onto a flexible 10-bit digital port as
shown in Figure 10. The digital video port consists of a program-
mable 10-bit digital Data Out Bus (d[9:0]) and three programma-
ble synchronisation signals (hsync, vsync, pclk).
By default the synchronisation signals are configured to operate
in “slave” mode. They can be programmed to operate in “mas-
ter” mode.
The following sections are a detailed description of the timing
and programming modes of digital video port.
The 10-bit digital video out bus can be tri-stated by asserting a
logic 0 on the oe pin or by writing a logic 1 to the TriState bit in
the DVBUSCONFIG3 register.
11.1
A programmable barrel shifter is provided to map the output of
the internal pixel data framer to the pins of the digital video bus
as illustrated in Figure 38.
The Bshift parameter in the DVBUSCONFIG2 register can be
used to program the number of bits that the digital pixel data is
shifted by.
This feature allows a programmable digital gain to be imple-
mented when connecting the sensor to 8 or 10 bit digital video
processing systems as illustrated in Figure 39.
KAC-9638
a) KAC-9638 Connected to a 10 bit Digital Image Processors
b) KAC-9638 Connected to a 8 bit Digital Image Processors
www.kodak.com/go/imagers 585-722-4385
TriState
Figure 39. Example of connection to 10/8 bit systems
Figure 37. Digital Pixel Data Out Bus Circuit Diagram
KAC-9638
KAC-9638
oe
Digital Video Data Out Bus (d[9:0])
Figure 38. Digital Video Bus Switching Modes
Internal Pixel Framer Output Barrel Shift Register
d9
9
8
d8
d[9:0]
d7
7
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
d9
d8
d7
d6
d5
d4
d3
d2
d6
6
d5
5
d4
4
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
(continued)
d3
3
Processor
Processor
d2
2
Digital
Image
Digital
Image
10 bit
8 bit
d1 d0
1
0
d[9:0]
21
11.2
In master mode the integrated timing and control block controls
the flow of data onto the 10-bit digital port, three synchronisation
outputs are provided:
The vsync, hsync and pclk signals can be tri-stated by assert-
ing a logic 0 on the oe pin or by writing a logic 0 to the TriState
bit in the DVBUSCONFIG3 register. (see figure 40) The tristat-
ing of Vsync, Hsync, and Pclk can be overriden by setting the
appropriate bit in the DVBUSCONFIG3 register.
11.3
The pixel clock output pin, pclk, is provided to act as a synchro-
nisation reference for the pixel data appearing at the digital
video out bus pins d[9:0]. This pin can be programmed to oper-
ate in two modes:
• In free running mode, (the PixClkMode bit of
• In data ready mode, (the PixClkMode bit of DVBUSCONFIG1
VsOveride, HsOverride, PclkOverride
DVBUSCONFIG1 register is set to a logic 0), the pixel clock
output pin, pclk, is always running with a fixed period. Pixel
data appearing on the digital video bus d[9:0] are synchro-
nized to a specified active edge of the clock as shown in Fig-
ure 41.
register is set to a logic 1), the pixel clock output pin pclk will
produce a pulse with a specified level every time valid pixel
data appears on the digital video bus d[9:0] as shown in Fig-
ure 42.
Figure 40. hsync,vsync and pclk output circuit diagram
TriState
invalid pixel data
invalid pixel data
pclk
hsync
vsync
oe
Synchronisation Signals in Master Mode
Pixel Clock Output Pin (pclk) (Master Mode)
vsync,hsync,pclk
Figure 41. pclk in Free Running Mode
pclk
d[9:0]
pclk
d[9:0]
pclk
d[9:0]
pclk
d[9:0]
Figure 42. pclk in Data Ready Mode
b) pclk active edge positive (default)
is the pixel clock output pin.
is the horizontal synchronisation output signal.
is the vertical synchronisation output signal.
a) pclk active edge negative
a) pclk active edge negative
b) pclk active edge positive
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vsync,hsync,pclk