edd51321dbh-ts Elpida Memory, Inc., edd51321dbh-ts Datasheet - Page 28

• Manufacturer Part Number: edd51321dbh-ts
• Description: 512m Bits Ddr Mobile Ram
• Manufacturer: Elpida Memory, Inc.

Write Operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst write is defined
by the column address, the bank select address (See “Pin Function”) in the cycle when the write command is issued.
DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first
rising edge of DQS, DQS must be set to low. tWPST after the last falling edge of DQS, the DQS pins can be
changed to high-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is
referred as write postamble.
Preliminary Data Sheet E1398E31 (Ver. 3.1)
Command
DQS
DQ
Address
/CK
CK
Command
DQS
NOP
/CK
DQ
CK
READ
Row
ACT
t0
BL = 2
BL = 4
BL = 8
tRCD
t0.5
NOP
t1
Read Operation (/CAS Latency)
tWPRES
tRPRE
Column
WRIT
t1.5
Write Operation
tWPRE
tAC,tDQSCK
t2
in0
in0
in0
28
t2.5
in1
in1
in1
NOP
t3
out0
in2
in2
t3.5
in3
in3
tWPST
out1
in4 in5
t4
out2
NOP
t4.5
out3
in6
EDD51321DBH-TS
tRPST
t5
in7
t5.5
BL: Burst length
VTT
VTT