edd51321dbh-ts Elpida Memory, Inc., edd51321dbh-ts Datasheet - Page 37

• Manufacturer Part Number: edd51321dbh-ts
• Description: 512m Bits Ddr Mobile Ram
• Manufacturer: Elpida Memory, Inc.

A Write Command to the Consecutive Read Command Interval: To Interrupt the Write Operation
1. Same
2. Same
3. Different
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
WRITE to READ Command Interval (Same bank, same ROW address)
Preliminary Data Sheet E1398E31 (Ver. 3.1)
Command
Destination row of the consecutive read
command
Bank
address
DQS
/CK
DM
DQ
CK
operation in this case.
Row address State
Same
Different
Any
WRIT
t0
READ
ACTIVE
—
ACTIVE
IDLE
in0
Data masked
t1
in1
[WRITE to READ delay = 1 clock cycle]
in2
t2
Operation
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
—*
1
1
t3
37
out0 out1
t4
out2
t5
NOP
out3
t6
EDD51321DBH-TS
High-Z
High-Z
t7
t8
BL = 4
CL = 3