DS2174 MAXIM [Maxim Integrated Products], DS2174 Datasheet
DS2174
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DS2174 Summary of contents
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... DS2174QN 44-Pin PLCC -40°C to +85°C DESCRIPTION The DS2174 enhanced bit error rate tester (EBERT software-programmable test-pattern generator, receiver, and analyzer capable of meeting the most stringent error-performance requir ements of digital transmission facilities. It features bit-serial, nibble-parallel, and byte-parallel data interfaces, and generates and uniquely synchronizes to pseudorandom patterns of the form 2 values from 1 to 32, and user-defined repetitive patterns of any length up to 512 octets ...
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... POWER-UP SEQUENCE..............................................................................................................6 1.7 DETAILED PIN DESCRIPTION..................................................................................................8 2. PARALLEL CONTROL INTERFACE ........................................................................................10 3. CONTROL REGISTERS ...............................................................................................................11 3.1 STATUS REGISTER...................................................................................................................15 3.2 PSEUDORANDOM PATTERN REGISTERS ...........................................................................15 3.3 TEST REGISTER ........................................................................................................................17 3.4 COUNT REGISTERS ..................................................................................................................17 4. RAM ACCESS .................................................................................................................................18 4.1 INDIRECT ADDRESSING ......................................................................................................... OPERATION ............................................................................................................................ TIMING CHARACTERISTICS .............................................................................................20 6.1 PARALLEL PORT ......................................................................................................................20 6.2 DATA INTERFACE....................................................................................................................22 7. MECHANICAL DIMENSIONS ....................................................................................................24 TABLE OF CONTENTS DS2174 ...
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... Table 3-1: MODE SELECT ..................................................................................................................13 Table 3-2: ERROR BIT INSERTION...................................................................................................13 Table 3-3: PSEUDORANDOM PATTERN GENERATION...............................................................16 Table 5-1: RECOMMENDED DC OPERATING CONDITIONS.......................................................19 Table 5-2: DC CHARACTERISTICS...................................................................................................19 Table 6-1: PARALLEL PORT READ TIMING...................................................................................20 Table 6-2: PARALLEL PORT WRITE TIMING .................................................................................21 Table 6-3: TRANSMIT DATA TIMING..............................................................................................22 Table 6-4: RECEIVE DATA TIMING .................................................................................................23 LIST OF FIGURES LIST OF TABLES DS2174 ...
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... Pattern Generation Polynomial Generation The DS2174 has a tap select register that can be used as a mask to tap bits in the feedback path of the polynomial generator. It also features a seed register that can be used to preload the polynomial generator with a seed value. This is done on the rising edge Control Register 1. ...
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... Generating Errors Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted data stream. Injecting errors allows users to stress communication links and to check the functionality of error monitoring equipment along the path DS2174 ...
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... Power-Up Sequence On power-up, the registers in the DS2174 are in a random state. The user must program all the internal registers to a known state before proper operation can be ensured. ...
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... Transmit Serial Data or LSB of Transmit Nibble or Byte Data Transmit Data Nibble or Byte Transmit Data Nibble or Byte Transmit Data Nibble or Byte Transmit Data Byte Transmit Data Byte Transmit Data Byte Transmit Data Byte Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I DS2174 ...
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... Active-low signal. Must be low to read from the part. Signal Name: WR Signal Description: Write Strobe Signal Type: Input Active-low signal. Must be low to write to the part. Signal Name: TEST Signal Description: TEST Input Signal Type: Input (with internal 10k? pullup) Test Input. Should be left floating or held high DS2174 ...
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... TDAT4. Transmit data bit 4 in byte mode TDAT5. Transmit data bit 5 in byte mode TDAT6. Transmit data bit 6 in byte mode TDAT7. Transmit data bit 7 in byte mode Signal Name Signal Description: Data I/O Signal Type: I/O Parallel data pins DS2174 ...
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... REGISTER NAME Control Register 1 Control Register 2 Control Register 3 Control Register 4 Status Register Tap/Seed Register 0 Tap/Seed Register 1 Tap/Seed Register 2 Tap/Seed Register 3 TEST Register Count Register 0 Count Register 1 Count Register 2 Count Register 3 Count Register 4 Count Register DS2174 ...
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... Pseudorandom pattern 1 = Repetitive pattern LSB/MSB. LSB 0 = Repetitive pattern data is transmitted/received MSB first 1 = Repetitive pattern data is transmitted/received LSB first Transmit Load. A rising edge causes the transmit shift register loaded with the seed value. LPBK QRSS PS DESCRIPTION DS2174 (LSB) LSB TL ...
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... Single Bit Error Insert. A rising edge causes the device to insert a single error in SBE the outbound data. Must be cleared by the user. EIR2 Error Insert Bit 2. See Table 4. EIR1 Error Insert Bit 1. See Table 4. EIR0 Error Insert Bit 0. See Table 4. RINV SBE EIR2 DESCRIPTION DS2174 (LSB) EIR1 EIR0 ...
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... The bit that occurs after the rising edge of the SBE insert bit is inverted. In the case of the QRSS pattern, this could result in a string of 0’s longer than 14 bits; the DS2174 delays the erred bit by 1 clock cycle. Data in the nibble and byte modes is presented bits at a time. When in nibble or byte mode and ...
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... Select Bit for Registers 5h–8h. SEED 0 = Registers 5h–8h refer to tap select registers Registers 5h–8h refer to preload seed registers. PL8 Pattern Length Bit 8. Bit 8 of [8:0] End Address of Repetitive Pattern Data. PL4 PL3 PL2 DESCRIPTION R/W RAM COUNT DESCRIPTION DS2174 (LSB) PL1 PL0 (LSB) SEED PL8 ...
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... Status Register The status register contains information about the real-time status of the DS2174. When a particular event has occurred, the appropriate bit in the register is set All of the bits in this register (except for SYNC) operate in a latched fashion, which means that if an event occurs and a bit is set remains set until the user reads the register ...
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... DS2174 SEED0/1/2/3 TINV RINV ...
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... The bit counter is enabled regardless of synchronization. The status register bit BCOF is set when this 48-bit register overflows. The counter rolls over upon an overflow condition. The DS2174 latches the bit count into the bit count registers and clears the internal bit count when the LC bit in Control Register 1 is toggled from low to high ...
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... CR4.4. CR4.3 must remain set for the entire algorithm to properly increment the address pointer. START CR4.3=1 CR4.4 WRITE BYTE TO ADDRESS 0Fh LAST BYTE? YES WRITE n TO CR3 IF n > 255, THEN SET CR4.0 CR4 DONE DS2174 ...
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... TCLK = RCLK = 155MHz serial mode; outputs open-circuited or 80MHz byte mode < V < Applies to TDAT when tristated. 4) Applies to TDAT[0] and TCLKO. SYMBOL MIN TYP 3.0 3.3 DD (0°C to +70°C for DS2174Q; V -40°C to +85°C for DS2174QN; V SYMBOL MIN TYP - -500 ILP I - ...
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... RD Pulse Width DATA Output Delay After RD DATA Float Time After RD CS Hold Time After RD = Rising Edge = Falling Edge NOTES: 1) 50pF load VALID DATA (0°C to +70°C for DS2174Q; V -40°C to +85°C for DS2174QN; V SYMBOL MIN TYP t 5.0 SU(1) t 10.0 SU(2) t 10.0 H(1) t ...
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... A(3:0) Setup Time Before WR A(3:0) Hold Time After WR WR Pulse Width DATA Setup Time Before WR DATA Hold Time After WR CS Hold Time After WR t H( H(2) SU(3) VALID DATA (0°C to +70°C for DS2174Q; V ° -40°C to +85 C for DS2174QN; V SYMBOL MIN TYP t 5.0 SU(1) t 10.0 SU(2) t 10.0 H( ...
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... TDAT Output Delay After TCLKO NOTES: 1) 20pF load. 2) TDAT follows falling edge of TCLKO if CR4 rising edge if CR4 Guaranteed by design. t CYC t PWH t PWL OD(1) ° +70°C for DS2174Q; V -40°C to +85°C for DS2174QN; V SYMBOL MIN t 12.5 CYC t 5.0 PWH t 5.0 PWL t 6.45 CYC t 2.0 PWH t 2.0 ...
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... RCLK_EN Hold Time After RCLK RDAT(7:0) Setup Time Before RCLK RDAT(7:0) Hold Time After RCLK NOTES: 1) Guaranteed by design. t CYC t PWL IGNORE IGNORE IGNORE t t SU(1) H(1) ° (0°C to +70 C for DS2174Q; V -40°C to +85°C for DS2174QN; V SYMBOL MIN t 12.5 CYC t 5.0 PWH t 5.0 PWL t 6.45 CYC t 2.0 PWH t 2.0 ...
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... MECHANICAL DIMENSIONS DS2174 ...