DS2174 MAXIM [Maxim Integrated Products], DS2174 Datasheet - Page 15

• Manufacturer Part Number: DS2174
• Description: EBERT
• Manufacturer: MAXIM [Maxim Integrated Products]

3.1 Status Register
The status register contains information about the real-time status of the DS2174. When a particular event
has occurred, the appropriate bit in the register is set to a 1. All of the bits in this register (except for
SYNC) operate in a latched fashion, which means that if an event occurs and a bit is set to a 1, it remains
set until the user reads the register. For the BED, BCOF, and BECOF bits, they are cleared when read and
are not set again until the event has occurred again. For RLOS, RA0, and RA1 bits, they are cleared when
read if the condition no longer persists.
Status Register (Address = 4h)
3.2 Pseudorandom Pattern Registers
Note: Bit 1 of Control Register 4 determines if the addresses point to the tap select or seed registers.
The tap select register is used to select the length and tap positions for pseudorandom
generation/reception. Each bit that is set to a 1 denotes a tap at that location for the feedback path. The
highest bit location set to a 1 is the length of the shift register. All pattern lengths are available in bit
mode, patterns 2
in byte mode. The pattern generator generates all 1’s if the exponent in the polynomial is less than 4
(nibble mode) or 8 (byte mode).
For example, to transmit/receive 2
would be 0. Table 5 gives tap select and seed values for many pseudorandom patterns.
The seed value is loaded into the transmit shift register on the rising edge of TL (CR1.0).
Tap Select/Seed Value Registers (Address = 5h–8h)
(MSB)
BIT15
BIT23
BIT31
BIT7
SYMBOL
(MSB)
BECOF
SYNC
BCOF
RLOS
—
BED
RA1
RA0
—
BIT14
BIT22
BIT30
BIT6
4
Not Assigned. Could be any value.
Receive All 1’S. Set when 40 consecutive 1’s are received in pseudorandom mode.
Allowed to be cleared when a 0 is received.
Receive All 0’s. Set when 40 consecutive 0s are received in pseudorandom mode.
Allowed to be cleared when a 1 is received.
Bit Error Detection. Set when bit error count is non-zero. Cleared when read.
Bit Error Count Overflow. Set when the bit error counter overflows. Cleared when
read.
Bit Counter Overflow. Set when the bit counter overflows. Cleared when read.
Receive Loss of Sync. Set when the receiver is searching for synchronization.
Remains set until read once sync is achieved. This bit is latched.
Sync. Real-time status of the synchronizer. This bit is not latched.
RA1
- 1 and greater are available in nibble mode, and patterns 2
BIT13
BIT21
BIT29
BIT5
RA0
15
BIT12
BIT20
BIT28
BIT4
- 1 (O.151) BIT14 and BIT13 would be set to a 1. All other bits
BED
BIT11
BIT19
BIT27
BIT3
15 of 24
DESCRIPTION
BECOF
BIT10
BIT18
BIT26
BIT2
BCOF
BIT17
BIT25
BIT1
BIT9
8
- 1 and greater are available
RLOS
BIT16
BIT24
(LSB)
BIT0
BIT8
SYNC
(LSB)
DS2174