ch7301a ETC-unknow, ch7301a Datasheet - Page 16

• Manufacturer Part Number: ch7301a
• Description: Chrontel Ch7301 Dvi Output Device
• Manufacturer: ETC-unknow

CHRONTEL
16
Transfer Protocols (continued)
AAR[6:0]
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc and alternating operation.
CH7301 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7301 always acknowledges for writes (see Figure 9). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
Figure 10 shows two consecutive alternating write cycles. The byte of information, following the Register Address
Byte (RAB), is the data to be written into the register specified by AR[6:0]. If AutoInc = 0, then another RAB is
expected from the master device, followed by another data byte, and so on.
Note: The acknowledge is from the CH7301 (slave).
SD
SC
Condition
Start
Device ID
1 - 7
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7301. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
R/W*
By Master-Transmitter
I
8
2
C
acknowledge
CH7301
ACK
SD Data Output
SD Data Output
By the CH7301
9
Figure 10: Alternating Write Cycles
Figure 9: Acknowledge on the Bus
RAB
1 - 8
SC from
Master
acknowledge
CH7301
ACK
Condition
9
Start
Data
1 - 8
acknowledge
CH7301
1
ACK
9
RAB
1 - 8
2
not acknowledge
acknowledge
acknowledge
CH7301
ACK
201-0000-036 Rev 1.1, 3/20/2000
9
acknowledgment
8
clock pulse for
Data
1 - 8
acknowledge
CH7301
ACK
9
CH7301A
9
Condition
Stop