ch7301a ETC-unknow, ch7301a Datasheet - Page 21

• Manufacturer Part Number: ch7301a
• Description: Chrontel Ch7301 Dvi Output Device
• Manufacturer: ETC-unknow

Input Data Format Register
Bits 2-0 of register IDF select the input data format. See Input Interface on page 5 for a listing of available formats.
Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.
Connection Detect Register
The Connection Detect Register provides a means to determine the status of the DAC outputs and the DVI hot plug
detect pin. The status bits, DACT[2:0] correspond to the termination of the three DAC outputs. However, the values
contained in these STATUS BITS ARE NOT VALID until a sensing procedure is performed. Use of this register
requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The
detection sequence works as follows:
1) Set the power management register to enable all DAC’s.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 3
analog outputs are at steady state and no TV synchronization pulses are asserted.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and
the reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be
set if they are NOT CONNECTED.
4) Read the status bits. The status bits, DACT[2:0] now contain valid information which can be read to determine
which outputs are connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected
output.
Bit 5 of register CD can be read at any time to determine the level of the hot plug detect pin. When the hot plug
detect pin changes state, and the DVI output is selected, the TLDET* output pin will be pulled low signifying a
change in the DVI termination. At this point, the HPIR bit in register 1Eh should be set high, then low to reset the
hot plug detect circuit.
Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1] pin. A value of ‘1’
allows the hot plug detect circuit to pull the GPIO[1] / TLDET* pin low when a change of state has taken place on
the hot plug detect pin. A value of ‘0’ disables the interrupt signal. The GOENB1 control bit in register 1Eh should
be set to ‘1’ when HPIE2 is set to ‘1’.
CHRONTEL
DEFAULT:
DEFAULT:
201-0000-036 Rev 1.1, 3/20/2000
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
HPIE2 Reserved
R/W
R/W
IBS
7
0
7
0
R/W
R/W
6
0
6
0
DVIT Reserved
R/W
R
5
0
5
0
R/W
R
4
0
4
0
DACT2
R/W
R
3
0
3
0
DACT1
IDF2
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
R
2
0
2
0
DACT0
IDF1
R/W
CH7301A
R
1
0
1
0
IDF
1Fh
8
CD
20h
6
SENSE
IDF0
R/W
R/W
0
0
21
0
0