ch7301a ETC-unknow, ch7301a Datasheet - Page 25

• Manufacturer Part Number: ch7301a
• Description: Chrontel Ch7301 Dvi Output Device
• Manufacturer: ETC-unknow

CHRONTEL
Bit 3 of register TSTP controls the datapath reset signal. A value of ‘0’ holds the datapath in a reset condition,
while a value of ‘1’, places the datapath in normal mode. The datapath is also reset at power on by an internally
generated power on reset signal.
Bit 4 of register TSTP controls the IIC reset signal. A value of ‘0’ holds the IIC registers in a reset condition, while
a value of ‘1’, places the IIC registers in normal mode. The IIC registers are also reset at power on by an internally
generated power on reset signal.
Power Management Register
Register TSTP controls which circuitry within the CH7301 is operating, according to Table 12 below.
Table 12: Power Management
Version ID Register
Register VID is a read only register containing the version ID number of the CH7301. The MV default is ‘1’ when
the CH7301 is bonded out with Macrovision enabled, and ‘0’ when the CH7301 is bonded out with Macrovision
disabled.
201-0000-036 Rev 1.1, 3/20/2000
DEFAULT:
DEFAULT:
Circuit Block
DVI PLL
DVI Encode, Serialize and
Transmitter
VGA to TV Encoder
DAC 2
DAC 1
DAC 0
TV PLL, P-Out and BCO pins
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
DVIP
VID7
R/W
MV
R
7
0
7
DVIL
VID6
R/W
Is Operational When
DVIP = 1 & FPD != 1
DVIL = 1 & FPD != 1
N/A
DACPD2 != 1 & FPD != 1
DACPD1 != 1 & FPD != 1
DACPD0 != 1 & FPD != 1
FPD != 1
R
6
0
6
0
VID5
R/W
TV Reserved DACPD2 DACPD1 DACPD0
R
5
0
5
0
VID4
R/W
R
4
0
4
0
VID3
R/W
R
3
0
3
0
VID2
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
R
2
0
2
0
VID1
R/W
CH7301A
R
1
0
1
0
PM
49h
8
VID
4Ah
8
VID0
R/W
FPD
R
25
0
1
0
0