DS1244Y-120 DALLAS [Dallas Semiconductor], DS1244Y-120 Datasheet - Page 11

• Manufacturer Part Number: DS1244Y-120
• Description: 256K NV SRAM with Phantom Clock
• Manufacturer: DALLAS [Dallas Semiconductor]

NOTES:
1. WE is high for a read cycle.
2. OE = V
3. t
4. t
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
9. The expected t
10. t
11. t
12. RST (Pin1) has an internal pull–up resistor.
13. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
earlier of CE or WE going high.
buffers remain in a high impedance state during this period.
in a high impedance state during this period.
remain in a high impedance state during this period.
long as temperature exposure to the lithium energy source contained within does not exceed +85 C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
WP
DH
WR
DH
, t
and t
is specified as the logical AND of CE and WE. t
is a function of the latter occurring edge of WE or CE.
DS
IH
are measured from the earlier of CE or WE going high.
DS
or V
are a function of the first occurring edge of WE or CE.
IL
DR
. If OE = V
is defined as accumulative time in the absence of V
IH
during write cycle, the output buffers remain in a high impedance state.
WP
is measured from the latter of CE or WE going low to the
CC
with the clock oscillator running.
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DS1244Y