DS1244Y-120 DALLAS [Dallas Semiconductor], DS1244Y-120 Datasheet - Page 4

• Manufacturer Part Number: DS1244Y-120
• Description: 256K NV SRAM with Phantom Clock
• Manufacturer: DALLAS [Dallas Semiconductor]

PHANTOM CLOCK REGISTER DEFINITION Figure 2
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET and oscillator functions. Bit 4 controls the
RESET (pin 1). When the RESET bit is set to logic 1, the
RESET input pin is ignored. When the RESET bit is set
DS1244Y
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REGISTER
0
1
2
3
4
5
6
7
12/24
7
0
0
0
0
0
6
0
0
0
0
10 YEAR
0.1 SEC
10 SEC
10 MIN
10
OSC
5
0
A/P
10 DATE
MONTH
RST
HR
10
4
to logic 0, a low input on the RESET pin will cause the
Phantom Clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator.
When set to logic 1, the oscillator is off. When set to log-
ic 0, the oscillator turns on and the watch becomes op-
erational. These bits are shipped from the factory set to
a logic 1.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
which will always read logic 0. When writing these loca-
tions, either a logic 1 or 0 is acceptable.
3
0
2
SECONDS
MINUTES
MONTH
HOUR
0.01 SEC
YEAR
DATE
DAY
1
0
RANGE
(BCD)
00–99
00–59
00–59
01–12
00–23
01–07
01–31
01–12
00–99