acd80900 ETC-unknow, acd80900 Datasheet
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Data Sheet: ACD82124 24 Ports 10/100 Fast Ethernet Switch Controller Last Update: November 5, 1998 update information before starting a design ACD Confidential Material For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission. Rev.1.1.1.F Subject ...
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Table of Contents Section 1 General Description 2 Main Features 3 System Block Diagram 4 System Description 5 Functional Description 6 Interface Description 7 Register Description 8 Pin Description 9 Timing Description 10 Electrical Specifications 11 Packaging Appendix A1 Address ...
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... MAC addresses can be expanded from the built- 11K by the use of ACD’s external ARL chip (ACD80800 Address Resolution Logic). Advanced net- work management features can be supported with the use of ACD’s MIB (ACD80900 Management Informa- tion Base) chip. 3. SYSTEM BLOCK DIAGRAM FIFO ...
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... MIB (Management Information Base) interface. The MIB interface can be used to monitor all traffic activi- ties of the switch system. ACD’s supporting chip (the ACD80900) provides a full set of statistical counters to support both SNMP and RMON network management. The MIB interface can also be used by system de- signers to implement vendor-specific network manage- ment functionality ...
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FUNCTIONAL DESCRIPTION The MAC controller performs transmit, receive, and defer functions, in accordance to IEEE 802.3 and 802.3u standard specification. The MAC logic also handles frame detection, frame generation, error de- tection, error handling, status indication and flow con- ...
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A port’s MAC address register is cleared on power- up, hardware reset, or when the port enters into Link Fail state. If the SA aging option is enabled (Register- 16 bit 4) , the learned SA will be cleared if ...
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False Carrier Events If the RXER signal in the MII interface is asserted when the receive data valid (RXDV) signal is not asserted, the port is considered to have a false carrier event port has more than two ...
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This process is used to ensure that there are no dropped frames. Backpressure flow control can be disabled by setting the corresponding bit of the regis- ter-21. VLAN Support (register 23 & 24) The ACD82124 can support ...
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The order of all frames, unicast or broadcast, is strictly enforced by the ACD82124. The ACD82124 is designed with a non- blocking switching architecture capable ...
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LED Interface The ACD82124 provides a wide variety of LED indica- tors for simple system management. The update of the LED is completely autonomous and merely requires low speed TTL or CMOS devices as LED drivers. The status display is ...
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INTERFACE DESCRIPTION MII Interface (MII) The ACD82124 communicates with the external 10/ 100 Ethernet transceivers through standard MII inter- face. The signals of MII interface are described in table-6.1 : Table-6.1: MII Interface Signals Name Type Description PxCRS I ...
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Prior to any transaction, the ACD82124 will output thirty-two bits of ‘1’ preamble signal. After the preamble, a ‘01’ signal is used to indicate the start of the frame. For a write operation, the device will send a ...
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CPUIRQ is used to inform the CPU of some special status has been encountered by the ACD82124, like port partition, fatal system error, etc. By clearing the appropriate bit in the interrupt mask register, one can stop the specific source ...
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Table-11: LED Interface Signals Name Type Description LEDVLD0 O LED signal valid #0 LEDVLD1 O LED signal valid #1 nLEDCLK O 2.5 MHz LED clock nLED0 O Dual purpose indicator nLED1 O Dual purpose indicator nLED2 O Dual purpose indicator ...
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Configuration Interface There are 20 pins whose pull-up or pull-down state will be used as Power-On-Strobing configuration data (Reg- ister 25, & CFG0 - CFG19) to specify various working modes of the ACD82124. The CFG pins are shared with other ...
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REGISTER DESCRIPTION Registers in the ACD82124 are used to define the op- eration mode of various function modules of the switch controller and the peripheral devices. Default values at power-on are defined by the factory. The manage- ment CPU ...
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PAR register (register 3) The PAR register indicates the presence of the parti- tioned ports and the port ID. A port can be automati- cally partitioned if there is a consecutive false carrier event, an excessive collision or a jabber. ...
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ACT register (register 5) The ACT register indicates the presence of transmit or receive activities of each port since the register was last read. This register is automatically cleared after each read. Table-7.5 describes all the bits of this reg- ...
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INTMSK register (register 17) The INTMSK register defines the valid interrupt sources allowed to assert interrupt request pin. Table-7.17 lists all the bits of this register. Table-7.17: INTMSK Register Bit Description Enable "system initialization 0 completion" to interrupt Enable "internal ...
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CPU can assign link status for each port. Table-7.19 describes all the bit of this register. nFWD register (register 20) The nFWD register defines the forwarding mode of each port. Under forwarding mode, a port can forward Table-7.19: ...
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The nBP register defines back-pressure flow control capability for each port. Table-7.21 describes all the bit of this register. Table-7.21: nBP Register Bit Description 0 - Port 0 back-pressure scheme enabled Port 0 ...
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PVID registers (register 23) The PVID registers assign VLAN IDs for each port. There are 24 PVID registers, one for each port. A PVID consists of 4 bits, each corresponding to one of the 4 VLANs. A port can belong ...
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Table-7.25: POSCFG Register Bit 3:0 8 timing adjustment levels for SRAM Read data latching: 0000 - no delay 0001 - level 1 delay 0011 - level 2 delay 0101 - level 3 delay 0111 - level 4 delay 1001 - ...
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Table-7.26: FdEn Register Bit 0 - Port 0 & 1 each in Half-Duplex mode Port 0 & 1 paired into ONE Full-Duplex-Capable port 0 - Port 2 & 3 each in Half-Duplex mode Port ...
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Table-7.27 describes all the bits of this register. RVSMII register (register 28) The RVSMII register defines the reversed MII mode for each port. Table-7.28 describes all the bits of this register. Table-7.28: RVSMII register Bit Description 0 0 ...
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... ARLCLK relative to the transition edge of the data sig- nals. The ARLCLK provides reference timing for sup- porting chips, such as the ACD80800 and the ACD80900, which need to snoop the data bus for cer- tain activities. Table-7.31 describes all the bits of this register. ...
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PIN DESCRIPTIONS Pin Diagram Bottom View ...
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Pin List By Location: Part 1 Signal I/O Pin Pin Name Type A01 P23RXD0R I C13 A02 VDD C14 A03 P23T XD2R O C15 A04 P22RXD3R I C16 A05 P22RXE RR I C17 A06 P22T XD1R O C18 A07 P22T ...
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Pin List By Location: Part 2 Signal I/O Pin Pin Name Type T 01 DAT A28 I/ O AB01 T 02 DAT A27 I/ O AB02 T 03 ADDR5 O AB03 T 04 ADDR14 O AB04 T 05 VDD AB05 ...
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Pin List By Name (With Voltage Rating): Part 1 Signal Signal Pin I/O Type Name Name ADDR0 H03 3.3V O DAT A41 ADDR01 J03 3.3V O DAT A43 ADDR02 K03 3.3V O DAT A44 ADDR03 L 03 3.3V O DAT ...
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Pin List By Name (With Voltage Rating): Part 2 Signal Signal Pin I/O Type Name Name P12T XD1 P27 3.3V O P17RXE R P12T XD2 P28 3.3V O P17T XCL K P12T XD3 P29 3.3V O P17T XD0 P12T XE ...
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TIMING DESCRIPTION MII Receive Timing RXD[3: RX_DV, RXD, RX_ER setup time t2 RX_DV, RXD, RX_ER hold time MII Transmit Timing TXCLK TXEN TXD[3:0] t1 ...
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Reversed MII Receive Timing RXD[3: RXDV, RXD setup time T2 RXDV, RXD hold time Reversed MII Transmit Timing TXCLK TXD[3:0] T# Description: t1 RXDV, RXD ...
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Reversed MII Packet Timing (Start of Packet RXD[3:0] Reversed MII Packet Timing (End of Packet RXD[3:0] T# Desciption t1 PXD to RXDV ...
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PHY Management Read Timing PHY Management W rite Timing Description MIN TYP MAX UNIT t1 MDIO setup time MDC cycle ...
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ead T im ing ead T im ing ...
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CPU Com m and Tim ing t1 idle state bit bit stop bit ARL Result Timing ...
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LED Signal Timing ...
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PACKAGING Pin - A1 o.56 Pin - A1 Top View FLLLLLSMAYYWW 40.00+/-0.20 Side View 0.60+/-0.05 2.33+/-0.13 39 ...
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Appendix-A1 Address Resolution Logic (The built-in ARL with 2048 MAC Addresses) 40 ...
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SUMMARY The internal Address Resolution Logic (ARL) of ACD’s switch controllers automatically builds up an address table and maps up to 2,048 MAC addresses into their associated port. It can work by itself without any CPU intervention in an ...
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FUNCTIONAL DESCRIPTION The ARL provides Address Resolution service for ACD’s switch controllers. Figure block diagram of the ARL. Traffic Snooping All Ethernet frames received by ACD’s switch control- ler have to be stored into memory buffer. ...
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INTERFACE DESCRIPTION CPU Interface The CPU can communicate with the ARL through the UART interface of the switch IC. The management CPU can send command to the ARL by writing into associ- ated registers, and retrieve result from ARL ...
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REGISTER DESCRIPTION ACD80800 provides a bunch of registers for the CPU to access the address table inside it. Command is sent to ACD80800 by writing into the associated registers. Before the CPU can pass a command to ACD80800, it ...
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The CfgReg is used to configure the way the ACD80800 works. The bit definition of CfgReg is described as: bit 0 - disable address aging bit 1 - disable address lookup bit 2 - disable DA cache bit 3 - ...
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COMMAND DESCRIPTION Command 09H Description: Add the specified MAC address into the address table. Parameter: Store the MAC address into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the ...
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Command 11H Description: Read next entry of address book. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of the address book entry pointed by Read Pointer will ...
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Command 50H Description: Read first locked entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first locked entry of the address book will be stored into ...