acd80900 ETC-unknow, acd80900 Datasheet - Page 13

• Manufacturer Part Number: acd80900
• Description: 24 Ports 10/100 Fast Ethernet Switch Controller
• Manufacturer: ETC-unknow

CPUIRQ is used to inform the CPU of some special
status has been encountered by the ACD82124, like
port partition, fatal system error, etc. By clearing the
appropriate bit in the interrupt mask register, one can
stop the specific source from generating an interrupt
request. Reading the interrupt source register retrieves
the source of the interrupt and clears the interrupt
source register.
ASRAM Interface
All received frames are stored into the shared memory
buffer through the ASRAM interface. When the desti-
nation port is ready to transmit the frame, data is read
from the shared memory buffer through the ASRAM
interface. The signals in ASRAM interface are de-
scribed in Table-6.8 .
Data is written into the ASRAM or read from the ASRAM
in 52-bit wide words. The data is a 48-bit wide value
and the control is a 4 bit-wide value. ADDR specifies
the address of the word, and DATA contains the con-
tent of the word. Bit 0 ~ 47 of DATA bus are used to
pass 48-bit frame data. Bit 48 are used to indicate the
start and end of a frame. Bit 49 ~ 51 are used to
indicate the length of actual data presented on DATA0
~ DATA47.
nOE and nWE are used to control the timing of read
or write operation respectively. nCSx selects the
ASRAM chip corresponding to the word address. The
timing requirement on ASRAM access is described in
the chapter-9 “Timing Description”.
ARL Interface
ARL interface provides a communication path between
the ACD82124 and an ARL device, which can provide
up to 8K of additional address lookup function. As the
ACD82124 receives a frame, the destination address
and source address of the frame are displayed on the
ARLDO data lines for the external ARL device. After
the external ARL finds the corresponding destination
port, it returns the result through the ARLDIx lines to
DATA0-DATA51
ADDR0-ADDR16
nOE
nWE
nCS0 - nCS3
Table-6.8: ASRAM Interface
Name
Type
I/O
O
O
O
O
memory data bus
memory address bus
output enable, low active
write enable, low active
chip select signals, low active.
Description
the ACD82124. The timing requirement on ARL sig-
nals is described in Chapter-9 “Timing Description.”
Table-6.9 shows the associated signals in ARL inter-
face.
The data signal is tapped from the DATA bus of ASRAM
interface. Since all data of the received frames will be
written into the shared memory through the DATA bus,
the bus can be used to monitor occurrences of DA
and SA values, indicated by the status signal of
ARLSTAT. Therefore, ARLD0 through ARLD51 are the
same signals of DATA0 through DATA47.
ARLDIR1 and ARLDIR0 are used to indicate the di-
rection of data on the ARLDO bus:
ARLSYNC is used to indicate port 0 is driving the DATA
bus. Since the bus is pre-allocated in time division
multiplexing manner, the ARL device can determine
which port is driving the DATA bus.
ARLSTAT are used to indicate the status of the data
shown on the first 48 bits of DATA bus. The 4-bit status
is defined as:
ARLDO0-RLDO51
ARLDIR1-ARLDIR0
ARLSYNC
ARLSTAT0-
ARLSTAT3
ARLCLK
ARLDI0 - ARLDI3
ARLDIV
Table-6.9: ARL Interface Signals
00: Idle
01: for receiving data
10: for transmitting data
11: Header
0000 - Idle
0001 - First word (DA)
0010 - Second word (SA)
0011 - Third through last word
0100 - Filter Event
0101 - Drop Event
0110 - Jabber
0111 - False Carrier/Deferred Transmission*
1000 - Alignment error/Single Collision*
Name
Type
O
O
O
O
O
I
I
ARL data output, shared with
DATA 0 - DATA 51
ARL data direction indicator
ARL port synchronization
ARL data state indicator
ARL clock
ARL data input
ARL input data valid
00 for idle
01 for receive
10 for transmit
11 for control
Description
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