acd80900 ETC-unknow, acd80900 Datasheet - Page 16

• Manufacturer Part Number: acd80900
• Description: 24 Ports 10/100 Fast Ethernet Switch Controller
• Manufacturer: ETC-unknow

7. REGISTER DESCRIPTION
Registers in the ACD82124 are used to define the op-
eration mode of various function modules of the switch
controller and the peripheral devices. Default values at
power-on are defined by the factory. The manage-
ment CPU (optional) can read the content of all regis-
ters and modify some of the registers to change the
operation mode. Table-7.0 lists all the registers inside
the switch controller.
INTSRC register (register 1)
The INTSRC register indicates the source of the inter-
rupt request. Before the CPU starts to respond to an
interrupt request, it should read this register to find out
the interrupt source. This register is automatically
cleared after each read. Table-7.1 lists all the bits of
this register.
SYSERR register (register 2)
The SYSERR register indicates the presence of sys-
Table-7.0: Register List
Address
32-63
6-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
INTSRC
SYSERR
PAR
PMERR
ACT
SYSCFG
INTMSK
SPEED
LINK
nFWD
nBP
nPORT
PVID
VPID
POSCFG
nPAUSE
DPLX
RVSMII
nPM
ERRMSK
CLKADJ
PHYREG
Name
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
16 Bit
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
24 Bit
4 Bit
5 Bit
19 Bit
24 Bit
24 Bit
5 Bit
24 Bit
8 Bit
4 Bit
16 Bit
Size
Depth
Reserved
Reserved
24
24
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
tem errors. It is automatically cleared after each read.
Table-7.2 lists all kind of system error.
Table-7.1: INTSRC Register
Bit
Table-7.2: SYSERR Register
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
8
Interrupt Source
Port Partition Indication
PHY Management Error
Port Avtivity
System Configuration
Interrupt Mask
Port Speed
Port Link
Port Forward Disable
Port Back Pressure Disable
Port Disable
Port VLAN ID
VLAN Dumping Port
Power-On-Strobe Configuration
Port Pause Frame Disable
Port Duplex Mode
Reversed MII Selection
Port PHY Management Disable
Error Mask
ARL Clock Delay Adjustment
Registers in PHY device, (REG# - 32)
System Error
System initialization completed
System error occurred
Port partition occurred
BIST failure indication
ARL Interrupt
Description
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Default
Default
0
0
0
0
0
0
0
0
0
16
0
0
0
0
0
0
0
0