ra8835 Topway Display, ra8835 Datasheet - Page 35

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ra8835

Manufacturer Part Number
ra8835
Description
Dot Matrix Lcd Controller
Manufacturer
Topway Display
Datasheet

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RAiO TECHNOLOGY INC.
Version 1.7
7-4 Static RAM
7-5 Supply Current during Display Memory Access
7-6 Oscillator Circuit
The figure below shows the interface between an 8Kx 8 static RAM and the RA8835 series. Note that
bus buffers are required if the bus is heavily loaded.
The 24 address and data lines of the RA8835 series cycle at one-third of the oscillator frequency, f
The charge and discharge current on these pins, I
exceeds I
Where C is the capacitance of the display memory bus, V is the operating voltage, and f is the
operating frequency. If V
per line:
To reduce current flow during display memory accesses, it is important to use low-power memory, and
to minimize both the number of devices and the parasitic capacitance.
The RA8835 series incorporates an oscillator circuit. A stable oscillator can be constructed simply by
connecting an AT-cut crystal and two capacitors to XG and XD, as shown in the figure below. If the
oscillator frequency is increased, CD and CG should be decreased proportionally. Note that the circuit
board lines to XG and XD must be as short as possible to prevent wiring capacitance from changing
the oscillator frequency or increasing the power consumption.
OPR
, it can be estimated by:
Note: If the bus loading is too much, use a bus buffer.
RA8835
VA13 toVA15
VA0 to VA12
VD0 to VD7
OPR
WRD
VWR
= 5.0V, f = 1.0 MHz, and the display memory bus capacitance is 1.0 pF
Figure 7-3: Static RAM Interface
I
VOP
IVOP
120 mA / MHz x pF
35/86
A-C
HC138
Note
C V f
Y
VOP
V
, is given by the equation below. When I
DD
CS1
CE2
A0 to A12
WR
OE
I/O1 to I/O8
Compatible
2764-pin
memory
Dot Matrix LCD Controller
www.raio.com.tw
RA8835
OSC
VOP
.

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