HSC-DAC-EVALCZ AD [Analog Devices], HSC-DAC-EVALCZ Datasheet - Page 15
HSC-DAC-EVALCZ
Manufacturer Part Number
HSC-DAC-EVALCZ
Description
10-/12-Bit, Low Power, Broadband MxFE
Manufacturer
AD [Analog Devices]
Datasheet
1.HSC-DAC-EVALCZ.pdf
(60 pages)
- Current page: 15 of 60
- Download datasheet (2Mb)
Figure 16. Typical Die Temperature Readback Error vs. Ambient Temperature
REF –38.23dBm
#AVG
LOG 10dB/
CARRIER POWER
PAVG
10
W1 S2
Figure 18. AD9961, Second and Third Harmonic Distortion vs. f
Figure 17. One-Carrier W-CDMA ACLR Performance, IF = ~21 MHz
CENTER 21.00MHz
#RES BW 30kHz
RMS RESULTS
100
–10
3.84000MHz
95
90
85
80
75
70
65
60
55
50
10
–2
–4
–6
–8
–25.07dBm/
–40 –35 –25 –15 –5
8
6
4
2
0
f
DAC
0
= 125 MHz, 1×, Digital Scale = 0 dBFS, TXVDD = 1.8 V
THIRD HARMONIC (dBc)
10
FREQ OFFSET REF BW
IDAC 1.8V CMOS
ATTEN 2dB
5.000MHz
10.00MHz
15.00MHz
SECOND HARMONIC (dBc)
IDAC 1.8V CMOS
20
TEMPER ATURE (°C)
5
VBW 300kHz
3.840MHz
3.840MHz
3.840MHz
15 25 35 45 55 65 75 85 95
f
OUT
30
(MHz)
–73.49
–72.90
–73.44
SWEEP 109.8ms (601pts)
dBc
40
LOWER
DC COUPLED
–98.57
–97.97
–98.51
dBm
SPAN 33.84MHz
EXT REF
50
–73.85
–73.11
–73.56
dBc
UPPER
60
OUT
–98.92
–98.19
–98.63
dBm
,
Rev. 0 | Page 15 of 60
Figure 20. SNR/SFDR vs. Analog Input Level, f
Figure 21. SNR/SFDR vs. Analog Input Level, f
Figure 19. AD9961, Second and Third Harmonic Distortion vs. f
100
100
100
95
90
85
80
75
70
65
60
55
50
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
0
–80
0
–80
0
125 MHz, 1×, Digital Scale = 0 dBFS, TXVDD = 3.3 V
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
SNR (dBFS)
–70
–70
SFDR (dBc)
SFDR (dBc)
THIRD HARMONIC (dBc)
10
SNR (dBc)
SNR (dBc)
IDAC 3.3V CMOS
–60
–60
20
–50
–50
f
OUT
f
f
IN
IN
–40
–40
SECOND HARMONIC (dBc)
(dBm)
30
(dBm)
(MHz)
IDAC 3.3V CMOS
–30
–30
AD9961/AD9963
IN
IN
= 10 MHz, f
= 70 MHz, f
40
–20
–20
50
–10
–10
ADC
ADC
= 100 MSPS
= 100 MSPS
OUT
60
, f
0
0
DAC
=
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