HSC-DAC-EVALCZ AD [Analog Devices], HSC-DAC-EVALCZ Datasheet - Page 7

• Manufacturer Part Number: HSC-DAC-EVALCZ
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: AD [Analog Devices]

Table 5. Digital Logic Level Specifications
Parameter
CMOS INPUT LOGIC LEVEL
CMOS OUTPUT LOGIC LEVEL
DAC CLOCK INPUT
DIRECT CLOCKING
DLL ENABLED
SERIAL PERIPHERAL INTERFACE
V
V
V
V
V
V
V
V
V
V
V
V
Differential Peak-to-Peak Voltage
Duty Cycle
Slew Rate
Clock Rate
Clock Rate
Maximum Clock Rate
Minimum Pulse Width High (t
Minimum Pulse Width Low (t
Setup Time, SDIO (Data In) to SCLK (t
Hold Time, SDI to SCLK (t
Data Valid, SDIO (Data Out) to SCLK (t
Setup Time, CS to SCLK (t
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
Logic High
Logic High
Logic High
Logic Low
Logic Low
Logic Low
Logic High
Logic High
Logic High
Logic Low
Logic Low
Logic Low
DH
S
)
)
LOW
HIGH
)
)
DS
DV
)
)
Conditions
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
DRVDD = 1.8 V
DRVDD = 2.5 V
DRVDD = 3.3 V
CLKP/CLKN inputs
DLL delay line output
Rev. 0 | Page 7 of 60
Min
1.2
1.7
2.0
1.35
2.05
2.4
200
45
0.1
0.1
100
50
10
10
5.0
5.0
5.0
Typ
400
Max
0.5
0.7
0.8
0.4
0.4
0.4
CLK33V
55
200
310
5.0
AD9961/AD9963
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV p-p diff
%
V/ns
MHz
%
MHz
MHz
ns
ns
ns
ns
ns
ns