UPD77110GC NEC [NEC], UPD77110GC Datasheet - Page 31

• Manufacturer Part Number: UPD77110GC
• Description: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
• Manufacturer: NEC [NEC]

operation mode and operating clock is as follows:
multiple so that the multiplied frequency falls within the specified PLL lock frequency range.
the output division ratio so that the frequency m/n times the external input clock supplied to the DSP falls within the
specified operating frequency range of the DSP.
to 16 and supplies the divided clock to the internal circuitry. Specify the mask option of the HALT division ratio so
that necessary division can be performed.
from the CLKOUT pin can be specified. Specify the mask option as necessary.
the CLKOUT pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%).
8.2 WAKEUP Function
restored after the STOP mode has been released. If the WAKEUP pin is used, however, the status before the STOP
mode is set can be retained and program execution can be resumed starting from the instruction after the STOP
instruction.
functions as an interrupt pin. The pin functions as the WAKEUP pin only in the STOP mode (if this pin is asserted
active in the STOP mode, it is used only to release the STOP mode, and execution does not branch to an interrupt
vector).
8.3 Mask Option Equivalent Function of PD77110
manner as the PD77111 and 77112. However, an external pin on the PD77110 has a function equivalent to the
mask option. Care must be exercised when using the PD77110, including when it is used to emulate the PD77111
and 77112.
When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each
The PLL control circuit multiplies the input clock by an integer from 1 to 16. Specify the mask option of the PLL
The output divider divides the clock multiplied by the PLL by an integer from 1 to 16. Specify the mask option of
The HALT divider functions only in the HALT mode. It divides the clock of the output divider by an integer from 1
Whether the clock supplied to the internal circuitry of the DSP (internal system clock) is “output” or “not output”
If an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from
The WAKEUP pin can be used to release the STOP mode as well as a hardware reset.
If the STOP mode is released by means of a hardware reset, the status before the STOP mode was set cannot be
Whether the WAKEUP pin is used to release the STOP mode can be specified by a mask option.
When the WAKEUP function is specified valid, the WAKEUP pin is multiplexed with the INT4 pin and it usually
Because the PD77110 does not have mask options, the multiple of the PLL cannot be specified in the same
Normal operation mode
HALT mode
STOP mode
Operation Mode
Data Sheet U12801EJ4V0DS00
m/n times external input clock
m/n/l times external input clock
Stopped
Clock Supplied Inside DSP
PD77110, 77111, 77112
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