PLL500-10 PhaseLink (PLL), PLL500-10 Datasheet - Page 2

• Manufacturer Part Number: PLL500-10
• Description: , Low Phase Noise Vcxo ( 2.5MHz to 30MHz )
• Manufacturer: PhaseLink (PLL)

PAD DESCRIPTION
See also pad coordinates table at the end of this document.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
Name
XOUT
GND
VDD
CLK
SEL
VIN
XIN
OE
Number
PARAMETERS
1
2
3
4
5
6
7
8
Type
O
P
P
I
I
I
I
I
Crystal output pin.
Frequency control voltage input pin.
Output Enable input pin. Tri-states output if low. Enables output if high.
Ground pin.
Output clock pin.
+3.3V VDD power supply pin.
Divider select input pin. Allows user to choose between divider by 2 or 1.
Crystal input pin.
Low Phase Noise VCXO (8MHz to 40MHz)
SYMBOL
V
V
T
V
CC
O
S
I
Description
Preliminary
MIN.
-
-
-
-65
-40
0.5
0.5
0.5
PLL500-10
V
V
MAX.
CC
CC
260
150
85
7
+
+
0.5
0.5
Rev 3/24/03 Page 2
UNITS
V
V
V
C
C
C