PLL502-12 PhaseLink (PLL), PLL502-12 Datasheet

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PLL502-12

Manufacturer Part Number
PLL502-12
Description
, 12-25MHz In, 96-200MHz Out, LVDS
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTION
The PLL502-12 is a monolithic low jitter and low
phase noise (-125dBc/Hz @ 10kHz offset) VCXO IC
with LVDS output, for 96MHz to 200MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
F
range of applications, including 155.52MHz for
SONET.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
XIN
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
Low phase noise output for the 96MHz to
200MHz range (-125 dBc at 10kHz offset).
LVDS output.
12 to 25MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
Wide pull range (min. +/-190 ppm)
3.3V operation.
Available in 16 Pin TSSOP or SOIC.
x 8. This makes the PLL502-12 ideal for a wide
XOUT
XIN
Reference
VARICAP
Divider
XTAL
VIN
OSC
Comparator
Divider
Phase
VCO
Charge
Pump
Loop
Filter
VCO
OE
PIN CONFIGURATION
CLKBAR
CLK
OE (Pin 5)
1 (Default)
XOUT
0
GND
GND
VDD
VDD
XIN
VIN
OE
Preliminary
1
2
3
4
5
6
7
8
F
OUT
Tri-state
Output enabled
= F
XIN
PLL502-12
x 8
Output State
16
15
14
13
12
11
10
9
Rev 7/15/02 Page 1
VDD
GND_BUF
CLKBAR
VDD_BUF
CLK
GND_BUF
GND
GND

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PLL502-12 Summary of contents

Page 1

... LVDS output, for 96MHz to 200MHz output range. It allows the control of the output frequency with an input voltage (VIN), using a low cost crystal. The chip provides a pullable output at a frequency This makes the PLL502-12 ideal for a wide XIN range of applications, including 155.52MHz for SONET. BLOCK DIAGRAM ...

Page 2

... I Frequency control voltage input pin. P GND Power connectors. P GND connector for output buffers. O True clock output pin. P +3.3V Power supply connector for output buffers. O Complementary clock output pin. SYMBOL PLL502-12 Preliminary Description MIN. MAX 0 0.5 V 0.5 ...

Page 3

... CONDITIONS From power valid T VCXOSTB 25MHz; XIN XTAL C /C < 250 VCON 3.3V 0V VCON 3.3V, -3dB CONDITIONS I LVDS 1.25V (LVDS) PLL502-12 Preliminary MIN. TYP. MAX. UNITS 12 25 MHz 9.5 250 30 MIN. TYP. MAX. UNITS 10 380 ppm ppm 190 5 10 115 ppm/V 2000 25 MIN ...

Page 4

... 100 OH L (see figure GND out DD I OXD OSD PLL502-12 Preliminary MIN. TYP. MAX. UNITS 9 TBM 3 4 -60 dBc/Hz -90 dBc/Hz -112 dBc/Hz -125 dBc/Hz -123 dBc/Hz MIN. TYP. MAX. UNITS 247 355 454 - ...

Page 5

... CONDITIONS R = 100 (see figure LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL502-12 Preliminary MIN. TYP. MAX. 0.2 0.7 1.0 0.2 0.7 1.0 LVDS Switching Test Circuit OUT C = 10pF L V DIFF C = 10pF L OUT 80% 20 Rev 7/15/02 Page 5 UNITS ns ...

Page 6

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL502- PLL502-12 Preliminary REVISION CODE (when applicable) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP Rev 7/15/02 Page 6 ...

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