PLL520-05 PhaseLink (PLL), PLL520-05 Datasheet
PLL520-05
Related parts for PLL520-05
PLL520-05 Summary of contents
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... OUTPUT ENABLE LOGICAL LEVELS OE Part # Q Q PLL520-08 PLL520-05 PLL520-06 PLL520-07 PLL520-09 OE input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/-07/-09 Universal Low Phase Noise IC’s PIN CONFIGURATION (Top View) VDD 1 16 SEL0^ XIN 2 15 SEL1^ ...
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... Note: SEL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 3x3mm QFN* Type Pin number 13 I Crystal in connector. ...
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... VCXO Tuning Characteristic VCON input impedance VCON modulation BW Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 SYMBOL SYMBOL CONDITIONS CX+ ...
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... To be measured 6. Phase noise specifications PARAMETERS FREQUENCY 155.52MHz Phase Noise relative to carrier 622.08MHz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 SYMBOL CONDITIONS I PECL/LVDS/CMOS 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) CONDITIONS At 155 ...
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... Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive*) * Note: High Drive CMOS is available on PLL520-06 through DRIVSEL selector input on pin 12. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 SYMBOL CONDITIONS -12mA (Standard drive) ...
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... Output Short Circuit Current 10. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT OUT 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 SYMBOL CONDITIONS 100 ...
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... PARAMETERS Clock Rise Time Clock Fall Time PECL Levels Test Circuit OUT 50 50 OUT OUT 80% 50% 20% OUT 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 CONDITIONS – 2V (see figure SYMBOL CONDITIONS ...
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... PIN Narrow SOIC, TSSOP ( mm ) SOIC Symbol Min. Max. A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 9.80 10.00 E 3.80 4.00 H 5.80 6.20 L 0.40 1.27 e 1.27 BSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 A1 0.65 BSC B e Universal Low Phase Noise IC’ Rev 10/29/02 Page 8 ...
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... LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 PLL520-05/-06/-07/-08/-09 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 ...