PLL601-15 PhaseLink (PLL), PLL601-15 Datasheet
PLL601-15
Related parts for PLL601-15
PLL601-15 Summary of contents
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... Advanced low power sub-micron CMOS process. 3.3V operation. Available in 8-Pin SOIC or TSSOP. DESCRIPTIONS The PLL601- low cost, high performance and low phase noise clock synthesizer. It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques for a fixed 5x multiplier. The chip accepts crystal or clock inputs ranging from 20 to 30MHz, and produces outputs clocks up to 150MHz at 3 ...
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... Low Phase Noise PLL Clock Multiplier Type O Clock output from VCO. Equals the input frequency times multiplier. P 3.3V Power Supply. Crystal input to be connected to 20-30MHz fundamental parallel mode crys- I tal (C =15pF). On chip load capacitors: No external capacitor required Crystal Connection. P Ground. PLL601-15 Preliminary Description Rev 01/08/02 Page 2 ...
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... CONDITIONS At 3.3V 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 With capacitive decoupling between VDD and GND With capacitive decoupling between VDD and GND 100Hz offset, 3.3V 1kHz offset, 3.3V 10kHz offset, 3.3V 100kHz offset, 3.3V PLL601-15 MIN. MAX. UNITS - 0 0.5 V 0.5 CC ...
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... For XIN pin -25mA 25mA -8mA Load SYMBOL CONDITIONS Parallel Fundamental Mode F XIN C (xtal) L PLL601-15 Preliminary MIN. TYP. MAX. 3.135 3.465 2 0.8 VDD/2 (VDD/2) 1 VDD/2 (VDD/2) 2.4 0.4 VDD-0.4 35 120 MIN. TYP. MAX Rev 01/08/02 Page 4 UNITS ...
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... Low Phase Noise PLL Clock Multiplier TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 2.90 3.10 4.30 4.50 6.20 6.60 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL601- PLL601-15 Preliminary TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP Rev 01/08/02 Page 5 ...