CY28443-3 SPECTRALINEAR [SpectraLinear Inc], CY28443-3 Datasheet
CY28443-3
Related parts for CY28443-3
CY28443-3 Summary of contents
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... SRCT0 / 100MT_SST SRCC0/100M C_SST VDD48 SRCC0 / 100MC_SST 27M Spread VDD48 DOT96T DOT96C VDD48 48M VDD48 27M Non-spread Tel:(408) 855-0555 Fax:(408) 855-0550 CY28443-3 SRC PCI REF DOT96 USB_48M LCD 27M Pin Configuration VDD 1 56 VSS 2 55 PCI3 ...
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... I A precision resistor is attached to this pin, which is connected to the internal current reference. O, DIF Differential CPU clock outputs. I SMBus-compatible SCLOCK. I/O SMBus-compatible SDATA 14.318-MHz crystal output. I 14.318-MHz crystal input. CY28443-3 Description PIN 15 PIN 17 PIN 18 DOT96C 100MT_SST 100MC_SST DOT96C SRCT0 SRCC0 SRCC0 TBD ...
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... Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description CY28443-3 Description PIN 15 PIN 17 PIN 18 DOT96C ...
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... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28443-3 Page ...
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... PCI5 Output Enable 0 = Disabled Enabled PCI4 PCI4 Output Enable 0 = Disabled Enabled PCI3 PCI3 Output Enable 0 = Disabled Enabled PCI2 PCI2 Output Enable 0 = Disabled Enabled RESERVED RESERVED CPU[T/C]2 CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z Enabled PCIF1 PCIF1 Output Enable 0 = Disabled Enabled CY28443-3 Description Description Description Page ...
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... CPU[T/C]0 CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted Tri-state when CPU_STP# asserted SRC[T/C] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted Tri-state when PD asserted CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted Tri-state when PD asserted CY28443-3 Description Description Description Page ...
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... Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Name 0:–0.5% (Peak to peak) 1: –1.0% (Peak to peak) 0: Down Spread 1: Center Spread RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 48-MHz Output Drive Strength 0 = Low High CY28443-3 Description Description Description Description Page ...
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... Allow control of SRC[T/C]9 with assertion of SW PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]11 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED, Set = 0 Allow control of SRC[T/C]8 with assertion of SW PCI_STP Free running Stopped with PCI_STP# CY28443-3 Description Description Description Page ...
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... PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low High PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low High PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low High Name RESEREVD RESERVED RESERVED SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ SRC[T/C]5 stoppable by CLKREQ#A CY28443-3 Description Description Description Description Page ...
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... SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#B 1= SRC[T/C]4 stoppable by CLKREQ#B SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#B 1= SRC[T/C]3 stoppable by CLKREQ#B SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#B 1= SRC[T/C]2 stoppable by CLKREQ#B SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#B 1= SRC[T/C]1 stoppable by CLKREQ#B CY28443-3 Description Description Page ...
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... AT Parallel The CY28443-3 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28443-3 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm perfor- mance ...
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... Figure example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. Tstable <1 Tdrive_PWRDN# REF <300 s, > 200 mV Figure 5. Power-down Deassertion Timing Waveform CY28443-3 Page ...
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... Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Figure 6. CPU_STP# Assertion Waveform Tdrive_CPU_STP > 200 mV Figure 7. CPU_STP# Deassertion Waveform CY28443-3 Page ...
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... PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transi- ). (See tions to a high level. SU Tsu Figure 10. PCI_STP# Assertion Waveform CY28443-3 1.8 ms 1.8 ms Page ...
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... Figure 11. PCI_STP# Deassertion Waveform 0.2-0.3 ms Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On Figure 12. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0. VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28443-3 Device is not affected, VTT_PWRGD# is ignored State Sample Inputs straps Wait for <1.8 ms Enable Outputs Page ...
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... SDATA, SCLK Typical Typical Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max load in low drive mode per Figure 14 @133 MHz PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY28443-3 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 16 Math averages Figure 16 CY28443-3 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – 300 ppm 9.997001 10 ...
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... Math averages Figure 16 See Figure 16. Measure SE Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V CY28443-3 Min. 250 – –0.3 – 9.997001 OX 9.997001 OX 9 ...
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... Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 16 Math averages Figure 16 See Figure 16. Measure SE CY28443-3 Min. = 0.175 to 175 OL – – – 660 –150 250 – –0.3 – 45 29.99100 29 ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28443-3 Min. Max 20.83125 20.83542 20.48125 21.18542 8.094 10.036 7.694 9.836 1.0 2.0 – 350 – ...
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... PCI/ USB Figure 16. 0.7V Differential Load Configuration CY28443-3 Measurement Point 5 pF Measurement Point 5 pF Measurement Point easurem ent P oint easurem ent P oint easurem ent P oint ...
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... TSSOP CY28443ZXC-3T 56-pin TSSOP – Tape and Reel Rev 1.0, November 20, 2006 Package Type CY28443-3 - Product Flow Commercial Commercial Commercial Commercial Page ...
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... PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.508[0.020] 0.762[0.030] 0°-8° SEATING PLANE DIMENSIONS IN INCHES MIN. .010 GAUGE PLANE 0.024 0.040 0°-8° CY28443-3 MAX. 0.100[0.003] 0.200[0.008] MAX. 0.005 0.010 Page ...