CY28410OC SPECTRALINEAR [SpectraLinear Inc], CY28410OC Datasheet
CY28410OC
Related parts for CY28410OC
CY28410OC Summary of contents
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Features • Compliant with Intel CK410 • Supports Intel P4 and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks Block ...
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Pin Definitions Pin No. Name 44,43,41,40 CPUT/C 36,35 CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 14,15 DOT96T, DOT96C 18 FS_A 16 FS_B/TEST_MODE 53 FS_C/TEST_SEL 39 IREF 54,55,56,3,4,5 PCI 9,10 PCIF 8 PCIF0/ITP_EN 52 REF 46 SCLK 47 SDATA 26,27 SRC4_SATAT, SRC4_SATAC 19,20,22,23,2 SRCT/C 4,25,31,30,33, 32 ...
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Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by ...
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Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave .... Stop Table 4. Byte Read and ...
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Byte 1: Control Register 1 Bit @Pup DOT_96T Byte 2: Control Register 2 Bit @Pup ...
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Byte 3: Control Register 3 (continued) Bit @Pup Byte 4: Control Register 4 Bit @Pup DOT96[T/ Byte 5: Control Register ...
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Byte 6: Control Register 6 (continued) Bit @Pup 2 Externally selected 1 Externally selected 0 Externally selected Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit Revision Code Bit Revision Code Bit ...
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Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
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This signal is synchronized internal to the device prior to powering down the clock synthe- sizer also an asynchronous input for powering up the system. When PD is asserted high, all clocks ...
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PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD _A = 2.0V S0 ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC (Mil-Spec 883E ...
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DC Electrical Specifications Parameter Description I Power-down Supply Current PD3.3V AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle ...
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AC Electrical Specifications Parameter Description T Rise/Fall Matching RFM T Rise Time Variation R T Fall Time Variation F V Voltage High HIGH V Voltage Low LOW V Crossing Point Voltage at 0.7V Swing OX V Maximum Overshoot Voltage OVS ...
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AC Electrical Specifications Parameter Description T Any PCI clock to Any PCI clock Skew Measurement at 1.5V SKEW T PCIF and PCI Cycle to Cycle Jitter CCJ DOT T DOT96T and DOT96C Duty Cycle DC T DOT96T and DOT96C Period ...
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Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB REF For Differential CPU, SRC and DOT96 Output Signals The following ...
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... Ordering Information Part Number Standard CY28410OC 56-pin SSOP CY28410OCT 56-pin SSOP – Tape and Reel CY28410ZC 56-pin TSSOP CY28410ZCT 56-pin TSSOP – Tape and Reel Lead-free (Planned) CY28410OXC 56-pin SSOP CY28410OXCT 56-pin SSOP – Tape and Reel CY28410ZXC 56-pin TSSOP CY28410ZXCT 56-pin TSSOP – ...
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Package Drawing and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear ...