CY28435OXCT SPECTRALINEAR [SpectraLinear Inc], CY28435OXCT Datasheet
CY28435OXCT
Related parts for CY28435OXCT
CY28435OXCT Summary of contents
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Features • Compliant to Intel CK410 • Supports Intel Prescott and Tejas CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks • 33 ...
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Pin Description Pin No. Name 1,7 VDD_PCI 2,6 VSS_PCI 3,55,56 DF/PCI 4 FS_E/PCI4 5 PCI 8 DF_EN/PCIF0 9 SRESET_EN/PCIF 1 10 PCIF2 17 VTT_PWRGD#/PD 11 VDD_48 12 USB48_0 18 FS_A 13 VSS_48 14,15 DOT96T, DOT96C 16 FS_B/USB48_1 19,20,22,23, SRCT/C 24,25,30,31, ...
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Pin Description (continued) Pin No. Name 53 FS_C/REF1 54 SRESET#/PCI0 Frequency Select Pins (FS_[A:E]) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and FS_E inputs prior to VTT_PWRGD# assertion (as seen ...
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Table 1. Command Code Definition Bit Block read or block write operation Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, ...
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Control Registers Byte 0: Control Register 0 Bit @Pup SRC[T/C]4_SATA RESERVED Byte 1: Control Register 1 Bit @Pup DOT_96T/C 5 ...
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Byte 2: Control Register 2 (continued) Bit @Pup 0 1 Byte 3: Control Register 3 Bit @Pup SRC[T/C]4_SATA RESERVED Byte 4: Control Register 4 ...
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Byte 5: Control Register 5 (continued) Bit @Pup 0 0 Byte 6: Control Register 6 Bit @Pup 7 0 TEST_SEL 6 0 TEST_MODE PCI, PCIF and SRC clock outputs except those set to free ...
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Byte 8: Control Register 8 (continued) Bit @Pup RESERVED Byte 9: Control Register 9 Bit @Pup Byte 10: ...
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Byte 11: Control Register 11 Bit @Pup 7 0 CPU_DAF_N7 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 Byte 12: Control Register 12 Bit @Pup 7 0 ...
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Byte 14: Control Register 14 (continued) Bit @Pup Recovery_N8 Byte 15: Control Register 15 Bit @Pup 7 0 Recovery Recovery Recovery Recovery Recovery N3 ...
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Figure 2. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the ...
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Dynamic Frequency Dynamic Frequency – Dynamic Frequency (DF technique to increase the CPU frequency dynamically from any starting value. The user selects the starting point, either by HW, FSEL, or DAF then enables DF. After that, DF will ...
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It is not recommended to enable overclocking and change the N values of both PLLs in the same SMBUS block write. Watchdog Timer The Watchdog timer ...
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PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down ...
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FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Rev 1.0, November 20, 2006 0.2-0.3mS W ait for Delay VTT_PW RGD# State 1 On ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V (SSC ...
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AC Electrical Specifications Parameter Description T CPUT/C Cycle to Cycle Jitter CCJ L Long Term accuracy ACC CPUT and CPUC Rise and Fall Times Rise/Fall Matching RFM T Rise Time Variation R T Fall ...
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AC Electrical Specifications Parameter Description Edge Rate Falling edge rate T Any PCI clock to Any PCI clock Skew SKEW T PCIF and PCI Cycle to Cycle Jitter CCJ DOT T DOT96T and DOT96C Duty Cycle DC T DOT96T and ...
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AC Electrical Specifications Parameter Description Edge Rate Rising edge rate Edge Rate Falling edge rate T REF Cycle to Cycle Jitter CCJ ENABLE/DISABLE and SET-UP T Clock Stabilization from Power-up STABLE Test and Measurement Set-up For PCI Single-ended Signals and ...
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... Figure 11. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free CY28435OXC 56-pin SSOP CY28435OXCT 56-pin SSOP – Tape and Reel CY28435ZXC 56-pin TSSOP CY28435ZXCT 56-pin TSSOP – Tape and Reel Rev 1.0, November 20, 2006 Figure 10 ...
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Package Diagrams 28 29 0.088 0.092 0.025 BSC 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy ...