mx98745 Macronix International Co., mx98745 Datasheet - Page 24

• Manufacturer Part Number: mx98745
• Description: 100 Base-tx/fx Repeater Controller
• Manufacturer: Macronix International Co.

M. Configuration Register (register #31) (R/W)
P/N:PM0427
Bit(s)
31.15
31.14
31.13:12
31.11
31.10
31.9
31.8
31.7
31.6
31.5
31.4:0
Name
Reserved
L40H80
Reserved
EECF
Reserved
MONITOR
INTARB
FLWSPEC
PXM
TXXMII
PHY[4:0]
Description
Reserved for further usage.
0:Internal arbiter will qualify EDENL for more than 40 ns.
Power on low.
After power on reset, Write 1 to this bit will not make EEPROM operation.
When EECF is low, then value on corresponding pins (known as hardwire
setting) will be latched by MX98745 and overwrite the default setting of
MX98745.
Force to High all the time.
machine through LED7..0
0 : Put MX98745 in normal mode.
1:Internal Arbitor function is enabled
Power on low.
than 128 times, two ports will be partitoned by MX98745 simultaneously.
0 : Those ports which Receive after Transmit will be partitioned.(Same as
MX98741) i.e. ports encounter transmit collision will be paritioned only.
Value on LED0 will be stored in this bit in case EECONF is 0.
0:MAC type MII for port0 value on LED1 will be stored at this bit after
power on reset. When TXXMII is set to 1, this bit has no effect.
Contents will not be overwritten by EEPROM.
0 : MII mode (4B) is programmed for port 0
After power on reset, value on LED2 will be stored on this bit. Contents
will not be overwritten while loading EEPROM.
When EECONF is set to 0 (Disabled), value on LED[7:3] will be stored in
these five bits at the rising edge of RESETL.
If EECONF is set to high, value from EEPROM will overwrite the hardwire
setting.
1:Internal arbiter will qualify EDENL for more than 80 ns.
Reserved for further usage.
Power on reset value of LDS0.
1 : Set XRC II to monitor mode and monitor serial output of internal state
0:Internal Arbitor function is disabled.
1 : Partition function meets IEEE 802.3u i.e. when two ports collide more
1:PCS type MII for port0
1 : TX port is programmed (5B) for port 0
Physical address of MX98745.
Table 6-13 Configuration Register Bit Definition
24
MX98745
REV. 1.4, JUL. 8, 1998
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W