mk68901 STMicroelectronics, mk68901 Datasheet
mk68901
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mk68901 Summary of contents
Page 1
... Modem control . Loop back mode . 68000 BUS COMPATIBLE 48 PIN DIP OR 52 PIN PLCC DESCRIPTION The MK68901 MFP (Multi-Function Peripheral combination of many of the necessary peripheral functions in a microprocessor system. Included are : Eight parallel I/O lines Interrrupt controller for 16 sources Four timers Single channel full duplex USART The use of the MFP in a system can significantly re- duce chip count, thereby reducing system cost ...
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... MFP that the CPU is acknowledging an interrupt. CS and IACk must not be as- serted at the same time. IEI : Interrupt Enable In (input, active low). IEI is used to signal the MK68901 MFP that no higher priority device is requesting in- terrupt service. IEO : Interrupt Enable Out (output, active low). ...
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... See figure 33. All chip ac- cesses are independent of the timer clock. TAI,TBI : Timer A, B inputs. Used when running the MK68901 timers in the event count or the pulse width measurement mode. The interrupt channels associated with 14 and 13 are used for TAI and TBI, respectively. Thus, ...
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... Each individual function in the MK68901 is provided with a unique interrupt vector that is presented to the system during the interrupt acknowledge cycle. The interrupt vector returned during the interrupt ac- knowledge cycle is shown in figure 6, while the vec- tor register is shown in figure 7 ...
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... There are 16 vector addresses generated internally by the MK68901, one for each of the 16 interrupt channels. The Interrupt Control Registers (figure 8) provide control of interrupt processing for all I/O facilities of the MK68901. These registers allow the program- Figure 5 : General Purpose I/O Registers. Figure 6 : Interrupt Vector. mer to enable or disable any or all of the 16 inter- ...
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... MK68901 Figure 7 : Vector Register. Figure 8 : Interrupt Control Registers. 6/33 V000354 V000355 ...
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... If no other channel is making a re- quest, INTR will go inactive. If the mask bit is re-en- abled, any pending interrupt is now free to resume its request unless blocked by a higher priority re- quest for service. IMRA and IMRB are also readable . A conceptual circuit of an interrupt channel is shown in figure 10. MK68901 7/33 ...
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... A higher prio- rity channel may still request an interrupt and be ac- Figure Conceptual Circuit of the MK68901 MFP Daisy Chaining. 8/33 knowledged. The in-service bit of a particular chan- nel may be cleared by writing a zero to the corre- sponding bit in ISRA or ISRB ...
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... VR. The four low order bits (bit 3-bit 0) are ge- nerated by the interrupting channel. To acknowledge an interrupt, IACK goes low, the IEI input must go low (or be tied low) and the MK68901 MFP must have an acknowledgeable interrupt pen- ding. The Daisy Chaining capability (figure 11) re- quires that all parts in a chain have a common IACK ...
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... MK68901 Figure 12 : Timer A and B Control Registers. * Unused bits : read as zeros. In the delay mode, the prescaler is always active. A count pulse will be applied to the main timer unit each time the prescribed number of timer clock cy- cles has elapsed. Thus, if the prescaler is program- med to divide by ten, a count pulse will be applied to the main counter every ten cycles of the timer clock ...
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... Figure 13 : Timer Data Registers ( and D). Figure 14 : Timer C and D Register. * Unused read as zeros. MK68901 V000360 V000361 11/33 ...
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... MK68901 Figure Conceptual Circuit of the MFP Timers in the Pulse Width Measurement Mode. Changing the prescale value with the timer running can cause the first Time Out pulse to occur at an in- determinate time, (no less than one nor more than 200 timer clock cycles times the number in the time constant register), but subsequent Time Out pulses will then occur at the correct interval ...
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... The Sync Word will also be repea- tedly transmitted when no other data is available for transmission. Moreover, the MK68901 allows strip- ping of all Sync Words received in synchronous o- peration. The handshake control lines RR (Receiver Ready) and TR (Transmitter Ready) allow DMA o- peration ...
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... MK68901 Figure 17 : USART Control Register (UCR). 16 When this bit is zero, data will be clocked into and out of the receiver and transmit- ter at the frequency of their respective clocks. When this bit is loaded with a one, data will be clocked into and out of the re- ceiver and transmitter at one sixteenth the frequency of their respective clocks ...
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... RSR, the recei- ver will turn off immediately. All flags in- cluding the F/S bit will be cleared one is written to this bit, normal receiver ope- ration is enabled. The receive clock has to be running before the receiver is en- abled. MK68901 V000364 15/33 ...
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... MK68901 There are two interrupt channels associated with the receiver. One channel is used for the normal Buffer Full condition, while the other channel is used whe- never an error condition occurs. Only one interrupt is generated per word received, but dedicating two channels allows separate vectors : one for the nor- mal condition, and one for an error condition ...
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... Low (”0” High 1 1 Loop-Connects transmitter output to receiver input, and TC to Receiver Clock (RC and SI are not used ; they are bypas- sed internally). In loop back mode, trans- mitter output goes high when disabled. Altering these two bits after Transmitter MK68901 17/33 ...
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... When executing block tranfers or data necessary to save any errors so that they can be checked at the end of a block. In order to save error conditions during data transfer, the MK68901 MFP interrupt controller may be used by enabling error in- terrupt for the desired channel (Receive error or Transmit error) and by masking these bits off ...
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... The user has to determine the parity of the sync word when the word length is not 8 bits. The MK68901 MFP does not add a parity bit to the sync word if the word length is less than 8 bits. The extra bit in the sync word is transmitted as the parity bit. ...
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... MK68901 MK68901 ELECTRICAL SPECIFICATIONS – PRELIMINARY ABSOLUTE MAXIMUM RATINGS Symbol T Temperature under Bias A T Storage Temperature Voltage on Any Pin with Respect to Ground I P Power Dissipation esses above those l ist ed under ”Absol ute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functi onal operation of the devi ce at these or any other condition above those indicated in the operational sec- ti ons of this specificati on is not implied ...
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... 300 + 300 110 90 MK68901 = Unit Fig. Note ns 21, 21, 21- 21,22 ns 21-24 ns 21- 21,23,24 ns 21, 3,6 ...
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... CS is latched internally, therefore if spec’s 1 and 24 are met then CS may be reasserted before the rising clock and still terminate the current bus cycle.The new bus cy- cle will be delayed by the MK68901 until all appropriate internal operations have completed. 6. Although CS and DTACK are synchronized with the clock, the data out during a read cycle is asynchronous to the clock, relying only on CS for timing ...
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... Minimum Inactive Time of TAI, TBI Notes : 1. Error may be cumul a tive if repetitively performed. 2. Error with respect INT if note 3 is true. OUT 3. Assuming it is possible for the timer to make an interrupt request immediately. MK68901 (tpsc + 4t + (2t + 100ns (tpsc + 6t + 100ns) CLK CLK + 0 to – (tpsc + 6t ...
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... MK68901 Figure 21 : Read Cycle. Figure 22 : Write Cycle. Note : CS and I ACK must be a funct ion of DS. 24/33 V000367 V000368 ...
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... Figure 23 : Interrupt Acknowledge (IEI low). Figure 24 : Interrupt Acknowledge Cycle (IEI high). Note : CS and I ACK must be a funct ion of DS. MK68901 V000369 V000370 25/33 ...
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... MK68901 Figure 25 : Interrupt Timing. Note : Active edge i s assumed the rising edge. Figure 26 : Port Timing. 26/33 V 000371 V000372 ...
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... Figure 27 : Receiver Timing. Figure 28 : Transmitter Timing. MK68901 V 000346 V000347 27/33 ...
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... MK68901 Figure 29 : Timer Timing. Figure 30 : Reset Timing. 28/33 V 000348 V000349 ...
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... 100pf 20k R = 470 180 1 Figure 33 : MK68901 MFP External Oscillator Components. MK68901 ORDER CODES Part Number PackageType 68901P04 Ceramic DIP 68901P05 Ceramic DIP 68901N04 Plastic DIP 68901N05 Plastic DIP 68901Q04 Plastic PLCC 68901Q05 Plastic PLCC Figure 32 : INTR Test Load. ...
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... MK68901 MK68901 48–PIN PLASTIC DUAL–IN–LINE PACKAGE (N) Millimeters Dim Min. Max. Min. A 61.468 62.738 2.420 B 14.986 16.256 .590 C 13.462 13.97 .530 D 3.556 4064 .140 E 0.381 1.524 .015 F 3048 3.81 .120 G 1.524 2.286 .060 H 1.186 1.794 .090 J 15.24 17.78 .600 K 0.381 0.533 .015 L 0.203 0.305 ...
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... MK68901 48–PIN CERAMIC DUAL–IN–LINE PACKAGE (P) Inches Dim Min. A 2.376 B 0.576 C 0.120 D 0.015 F 0.030 G 0.100 BSC J 0.008 K 0.100 L 0.590 0.040 Max. 2.424 0.604 0.160 0.021 0.055 0.013 0.165 0.616 10 0.060 MK68901 31/33 ...
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... MK68901 MK68901 52–PIN PLASTIC LEADED CHIP CARRIER (Q) Inches Dim Min. A .165 A .090 1 D .785 D .750 1 D .690 2 E .785 E .750 1 E .690 2 H .042 J .042 K .013 L .008 M .026 N/N .043 1 32/33 Max. .180 .130 .795 .756 .730 .795 .756 .730 .048 .048 .024 ...
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... MK68901 PIN CONNECTIONS PLCC DIP FUNC. 1 – R – TAO 16 14 TBO 17 15 TCO 18 16 TDO Note : NC – No Connection Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use ...