88e3016 Marvell Semiconductor, Inc., 88e3016 Datasheet - Page 18
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88e3016
Manufacturer Part Number
88e3016
Description
Integrated 10/100 Fast Ethernet Transceiver
Manufacturer
Marvell Semiconductor, Inc.
Datasheet
1.88E3016.pdf
(106 pages)
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2.1 Reduced Gigabit Media Independent Interface (RGMII)
The 88E3016 device supports the RGMII specification (Version 1.2a, 9/22/2000, version 2.0, 04/2002 - except
instead of HSTL, it supports 2.5V SSTL_2).
Figure 3: RGMII Signal Diagram
The interface runs at 2.5 MHz for 10 Mbps and 25 MHz for 100 Mbps. The TX_CLK signal is always generated by
the MAC, and the RX_CLK signal is generated by the PHY.
During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the
transition from the free running clock to a data synchronous clock domain. When the speed of the PHY changes,
a similar stretching of the positive or negative pulse is allowed. No glitching of the clocks is allowed during speed
transitions.
The MAC must hold TX_CTRL low until the MAC has ensured that TX_CTRL is operating at the same speed as
the PHY.
Doc. No. MV-S103164-00, Rev. --
Page 18
88E3016
Integrated 10/100 Fast Ethernet Transceiver
MAC
Document Classification: Proprietary Information
CONFIDENTIAL
RGMII Interface
RX_CTL
TX_CTL
RD[3:0]
TD[3:0]
RXC
TXC
TX_CLK
TX_CTRL
TXD[3:0]
RX_CLK
RX_CTRL
RXD[3:0]
PHY
Copyright © 2006 Marvell
May 4, 2006, Advance
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