TN1112 LATTICE [Lattice Semiconductor], TN1112 Datasheet - Page 2

• Manufacturer Part Number: TN1112
• Description: Input Hysteresis in Lattice CPLD and FPGA Devices
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Test Device:
I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on
Temperature: Room temperature
The plots below are measured with MachXO. A 680 Ω resistor is used in Method 1. The I/Os are configured as “bus-
hold”.
Figure 4. Test Setup
In the following figures, top trace represents outputs and bottom trace represents inputs. Persistence was set to 5
seconds for all waveforms.
External Input
Method 1
Method 2
Method 3
Circuit
None
ispMACH 4128V
Input Series
Resistor
4.7K Ω
100 Ω
100 Ω
100 Ω
1K Ω
1K Ω
1K Ω
A
—
680
Feedback Resistor or
B
Capacitor
100pF
10K Ω
560 Ω
33pF
33pF
1K Ω
—
—
—
—
2
In
with Bus-Hold Input
MachXO
Lattice CPLD and FPGA Devices
<100ns
220ns
800ns
700ns
700ns
t
2µs
6µs
5µs
2µs
5µs
RISE
Out
Input Hysteresis in
<100ns
155ns
300ns
350ns
350ns
600ns
1.5µs
1.9µs
1.5µs
t
FALL
7µs