TN1112 LATTICE [Lattice Semiconductor], TN1112 Datasheet - Page 4

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TN1112

Manufacturer Part Number
TN1112
Description
Input Hysteresis in Lattice CPLD and FPGA Devices
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Input Hysteresis in
Lattice Semiconductor
Lattice CPLD and FPGA Devices
Input Hysteresis
Figure 7 demonstrates the input signal with slow ramp rate virtually follow the ramp rate of MachXO output.
Figure 7. Input measured at Point B
Note “jump” at transition point.
Figure 8. Zoomed View of Rising Edge of Figure 7
Most digital circuitry is effectively linear in nature. The output normally swings from one extreme (VOL) to the other
(VOH). At threshold level a smallest amount of noise will cause the output to swing widely from one extreme to the
other.
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