TN1112 LATTICE [Lattice Semiconductor], TN1112 Datasheet - Page 5

• Manufacturer Part Number: TN1112
• Description: Input Hysteresis in Lattice CPLD and FPGA Devices
• Manufacturer: LATTICE [Lattice Semiconductor]

Input Hysteresis in
Lattice Semiconductor
Lattice CPLD and FPGA Devices
With a fast slew rate input, the signal will stay around the threshold region for a short time. With a slower signal,
which stays in the threshold region for a long time, the noise will have more time to reverse the signal direction.
Hysteresis is one common solution to this problem. Hysteresis means that the state of the output is not only depen-
dent on the state of the input but, also, on the immediate past history of the input. A Schmitt trigger adds hysteresis
to the input by creating different trip points for low-to-high and high-to-low transition. For the CPLDs and FPGAs
that do not have the Schmitt trigger input, the bus-hold latch with an external resistor works in a similar manner.
The bus-hold input circuitry works by sinking a small amount of current when it's below the threshold and sourcing
when it's above the threshold. This means that the input voltage tends to stay low when it's low and high when it's
high. If all of the I/Os on a bus go high impedance, the bus will tend to stay in the same state until an output turns
on.
If a resistor is inserted in series with the input, the change in current will result in change in the voltage seen at the
pin. This is what causes that jump. The optimum resistor value will cause enough Δ V to put the input well past the
threshold region so that noise will not be able to cause unwanted switching, but will not be so large as to exacer-
bate the noise or slow the signal.
Refer to Figure 9 for discussion of the 'jump'.
The voltage jump is 128mV at the output (Ch3) transition point.
When the input is below the threshold, the voltage across the resistor is 96mV and -32mV after the transition. In
other words, the input signal source must source 144µA (96mV/680 Ω ). When input A passes the threshold, the sig-
nal source sinks 47µA (-32mV/680 Ω ). At this point, any noise spike is unlikely to go back beyond the threshold.
Figure 9. Input Series Resistor and Hysteresis
Summary
As the data indicate, even with the very simple input series resistor used in Method 1 and the CPLD internal input
bus-hold latch, maximum input rise and fall times will extend to hundreds of nanoseconds to microseconds.
5