CS4294-JQ CIRRUS [Cirrus Logic], CS4294-JQ Datasheet
CS4294-JQ
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CS4294-JQ Summary of contents
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... FAX: (512) 445 7581 http://www.cirrus.com ® Audio/Docking Codec ’97 (AMC’97) DESCRIPTION The CS4294 ‘97 compatible Audio Codec designed for PC multimedia systems. Using the in- dustry leading CrystalClear™ delta-sigma and mixed signal technology, the CS4294 is ideal for PC 98-compliant desktop, notebook, and enter- tainment PCs, where high-quality audio features are required ...
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... Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trade- marks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service 2 CS4294 DS326PP4 ...
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... ANALOG HARDWARE DESCRIPTION ................................................................................. 30 7.1 Line-Level Inputs ............................................................................................................. 30 7.2 Microphone Level Inputs ................................................................................................. 30 7.3 Line Level Outputs ........................................................................................................... 31 7.4 Miscellaneous Analog Signals ......................................................................................... 31 7.5 Power Supplies ................................................................................................................ 32 8. PIN DESCRIPTIONS .............................................................................................................. 33 8.1 Digital I/O Pins ................................................................................................................. 33 8.2 Analog I/O Pins ................................................................................................................ 35 8.3 Filter and Reference Pins ................................................................................................ 36 8.4 Power Supplies ................................................................................................................ 37 9. PARAMETER AND TERM DEFINITIONS .............................................................................. 38 10. REFERENCES ...................................................................................................................... 39 11. PACKAGE DIMENSIONS .................................................................................................... 40 DS326PP4 ........................................................... 23 CS4294 3 ...
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... Table 2. Alternate Line-Out and Master Mono Attenuation ........................................................... 19 Table 3. Analog Mixer Input Gain Values...................................................................................... 19 Table 4. Stereo Volume Register Index ........................................................................................ 20 Table 5. Input Mux Selection......................................................................................................... 20 Table 6. 6 Channel Volume Attenuation........................................................................................ 24 Table 7. GPIO Input/Output Configuration .................................................................................... 27 Table 8. Slot Assignments............................................................................................................ 28 Table 9. Reg. 7Eh Defined Part ID’s ............................................................................................. 29 4 CS4294 DS326PP4 ...
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... Min A-D 0.91 A-D 0.91 A-D 0.091 (Note 4) D-A 0.91 FR A-A 20 D A-A 90 A-A 85 D-A 85 A-D 85 SNR D-A - THD+N A-A - D-A - A (Note 5) - (Note (Note 5) - (Note 5) - 2.0 refers to the digital output pin loading /680 pF load. AL CS4294-JQ Typ Max Min Typ Max 1.00 - 0.91 1.00 - 1.00 - 0.91 1.00 - 0.10 - 0.091 0.10 - 1.0 1.13 0.91 1.0 1.13 - 20,000 20 - 20,000 - 20,000 20 - 20,000 - 20,000 20 - 20,000 ...
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... V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 (for CS4294-KQ only) Line In, Aux, CD, Mic1 Line Out, Alternate Line Out All volume controls (AVss = DVss = 0 V) Symbol ...
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... T sync_high T sync_low isetup T ihold T irise T ifall (Note orise (Note ofall T s2_pdown T sync_pr4 T sync2clk (Note 5) T setup2rst (Note 5) T off series termination and pF. L CS4294 Min Typ Max Unit 1 120 - - 62 12.288 - MHz - 81 750 40.7 45 ...
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... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY BIT_CLK T orise SYNC T irise Figure 3. Codec Ready from Startup or Fault Condition 8 T rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd Figure 2. Clocks clk_high clk_low clk_period T T ifall T sync_high sync_low T sync_period CS4294 T rst2clk T ifall DS326PP4 ...
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... SDATA_OUT, SYNC BIT_CLK Slot 1 SDATA_OUT Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK DS326PP4 isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don’t Care T s2_pdown T sync_pr4 Figure 5. PR4 Powerdown T setup2rst T off Figure 6. Test Mode CS4294 T ihold T sync2clk Hi-Z 9 ...
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... The first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sam- pled active by the CS4294 (on the falling edge of BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame’ ...
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... RESET# signal. After being reset, the Co- dec is responsible for flagging the Controller that it is ready for operation after synchronizing its inter- nal functions. The AC-link signals may be refer- enced to either 5 Volts or 3.3 Volts. The CS4294 must use the same digital supply voltage as the Controller chip. Digital AC’97 ...
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... Input Mixer, stereo enhancement, and the PCM DAC output. The stereo output mix is sent to the LINE_OUT and ALT_LINE_OUT out- put pins of the CS4294. When the device is set to Mode 1 or the EAM bit in AC Mode Control (Index 5Eh) is set, the secondary DAC outputs are routed to ALT_LINE_OUT ...
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... If a Slot Valid bit is set, the named slot contains valid audio data. If the bit is clear, the slot will be ignored. The definition of each slot is determined by the basic operating mode selected for the CS4294. For more information, see the AC Mode Control (Index 5Eh) register. ...
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... GPIO Output Data. Output data is transferred to the GPIO pins every frame in Slot 12. 5.4 AC-Link Audio Input Frame In the serial data input frame, data is passed on the SDATA_IN pin FROM the CS4294 to the AC ’97 Controller. The data format for the input frame is very similar to the output frame. Figure 9 illustrates the serial port timing ...
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... The timing of power-up/reset events is discussed in detail in the Power Management section. 5.5.2 Warm AC ’97 Reset The CS4294 may also be reactivated when the AC- link is powered down (refer to the PR4 bit descrip- tion in the Power Management section Warm Reset. A Warm Reset allows the AC-link to be re- activated without losing information in the Codec’ ...
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... AC ’97 Register Reset The third reset mode provides a register reset to the CS4294. This is available only when the CS4294’s AC-link is active and the Codec Ready bit is set. The audio and extended codec subsections may be reset independently. Any write to Reset (Index 00h) ...
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... GP8 GP7 GS8 GS7 GW8 GW7 Gi8 GI7 1 1 EDM EAM DDM Table 1. Mixer Registers CS4294 ID4 MR5 MR4 MR3 MR2 MR1 MR0 MR5 MR4 MR3 ...
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... In Mode 1 the LINE_OUT volume is controlled by the Left Right Surround (Index 38h) register in place of Master Volume. 18 D11 D10 SE1 SE0 0 ID8 ID7 SE1 SE0 0 ID8 ID7 D10 ML2 ML1 ML0 CS4294 ID4 MR5 MR4 MR3 MR2 MR1 D1 ...
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... ML1 ML0 ML[5:0]/MR[5:0]/MM[5:0 Read 000000 000001 … 111111 D10 20dB Gain Level +12.0 dB +10.5 dB … +1.5 dB 0.0 dB -1.5 dB … -34.5 dB Table 3. Analog Mixer Input Gain Values CS4294 MR5 MR4 MR3 MR2 MR1 Gain Level 0 dB -1.5 dB ... -94 GN4 GN3 GN2 GN1 Mic Gain with 20dB = 1 +32 ...
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... Sx2 - Sx0 Record Source Not Available Not Available Table 5. Input Mux Selection GR4 GR3 GR2 Function SR2 MIC CD Input AUX Input Line Input Stereo Mix Mono Mix CS4294 D1 D0 GR1 GR0 D1 D0 SR1 SR0 DS326PP4 ...
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... The Spacial Enhancements is not available on the ALT_LINE output when the codec is in Mode 1 or EAM is set. See the AC Mode Control (Index 5Eh) register for more detail. DS326PP4 D10 GL2 GL1 GL0 D10 LPBK D10 CS4294 GR3 GR2 GR1 ...
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... ADC bits are status bits which, when set, indicate that a particular section of the Codec is ready. After the Controller receives the Codec Ready bit in Slot 0, these status bits must be checked before writing to any mixer registers. 22 D10 PR2 PR1 PR0 CS4294 REF ANL DAC DS326PP4 D0 ADC ...
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... D7 D6 SR9 SR8 SR7 SR6 D10 SR9 SR8 SR7 SR6 CDAC SR5 SR4 SR3 SR2 SR5 SR4 SR3 SR2 CS4294 D1 D0 VRA VRA SR1 SR0 D1 D0 SR1 SR0 23 ...
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... D10 LFE2 LFE1 LFE0 Mute LFE[5:0]/LSR[5:0] CNT[5:0]/RSR[5:0] Read 000000 000001 … 111111 Table 6. 6 Channel Volume Attenuation D10 Mute CS4294 SR5 SR4 SR3 SR2 SR1 SR5 SR4 SR3 SR2 SR1 D5 D4 ...
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... DS326PP4 D11 D10 D11 D10 PRD PRC PRB PRA EDAC2 EADC2 PRC PRB PRA EDAC1 EADC1 EREF EADC2 EADC1 EREF CS4294 GPIO GPIO 25 ...
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... SR9 SR8 SR7 SR6 D10 SR9 SR8 SR7 SR6 D10 Mute D10 Mute CS4294 SR5 SR4 SR3 SR2 SR1 SR5 SR4 SR3 SR2 SR1 ADC3 ADC2 D5 D4 ...
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... res GP8 GP7 GP6 Function Output Output Input Input Table 7. GPIO Input/Output Configuration D10 GS8 GS7 GS6 CS4294 GC5 GC4 GC3 res res GP5 GP4 GP3 res res CMOS drive Open drain Active Low ...
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... Default 0000h The CS4294 has the ability to generate a “wake up” cycle by a transition of a GPIO pin when the AC-Link has been powered down mask bit is set, a one being set in the corresponding GPIO Pin Status (Index 54h) will initiate a wake up interrupt. Bit 0 of SDATA_IN Slot 12 will be set indicating a GPIO interrupt. GPIO pins must be defined as “ ...
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... D10 PID2 D3 000 001 010 0 010 1 011 Table 9. Reg. 7Eh Defined Part ID’ PID1 PID0 1 RID2 Part Name CS4297 CS4297A CS4298 CS4294 CS4299 CS4294 RID1 RID0 29 ...
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... DAC out- put (if the POP bit is set). 6.8 k 6.8 k 6.8 k Figure 10. Line Inputs 30 All analog inputs to the CS4294, including CD_GND, should be capacitively coupled to the input pins. Since many analog levels can be as large RMS to attenuate the analog input ( which is the maximum voltage allowed for all the stereo line-level inputs: LINE_IN and AUX_IN ...
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... AGND 100 k 2.7 k AGND 0.068 µF X7R 220 pF 220 pF 6 µF 2 CGND AGND Figure 12. PC ‘99 Microphone Pre-amplifier +5 VA U1A 47 k MC33078D µ AGND AGND U1B MC33078D µ X7R 4 AGND 220 CS4294 MIC1 31 ...
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... The pins AVdd1 and AVdd2 supply power to all the analog circuitry on the CS4294. This 5 Volt analog supply should be generated from a voltage regulator (7805 type) connected to a +12 Volt supply. This helps isolate the analog cir- ...
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... SYNC - AC-link Serial Port Sync pulse, Input This signal is the serial port timing signal for the AC-link of the CS4294. Its period is the reciprocal of the sample rate of the CS4294, 48 kHz. This signal is generated by the AC ’97 Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the CS4294 PR4 powerdown state and is configured as a primary codec ...
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... SDATA_OUT - AC-link Serial Data Input Stream to AC ‘97, Input This input signal transmits the control information and digital audio output streams to be sent to the DACs. The data is clocked into the CS4294 on the falling edge of BIT_CLK. A series terminating resistor of 47 input. ...
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... CD_L and CD_R - Analog CD Source, Inputs These inputs form a stereo input pair to the CS4294 intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required ...
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... AUX_L and AUX_R - Analog Auxiliary Source, Inputs These inputs form a stereo input pair to the CS4294. The maximum allowable input (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground ...
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... DVdd1, DVdd2 - Digital Supply Voltage These pins provide the digital supply voltage for the AC-link section of the CS4294. These pins may be tied digital or to +3.3 V digital. The CS4294 and digital controller’s AC-link should share a common digital supply. DVss1, DVss2 - Digital Ground These pins are the digital ground connection for the AC-link section of the CS4294 ...
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... The number of bits in the output words to the DACs, and in the input words to the ADCs. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB defined as dB relative to full-scale. The “A” indicates an A weighting filter was used. 38 CS4294 ® DS326PP4 ...
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... Units in dB. PATHS A-D: Analog in, through the ADC, onto the serial link. D-A: Serial interface inputs through the DAC to the analog output. A-A: Analog in to Analog out (analog mixer). 10. REFERENCES Intel, Audio Codec ‘97 Component Specification, Revision 2.1, May 22,1998. http://developer.intel.com/pc-supp /platform/ac97/ DS326PP4 CS4294 39 ...
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... Controlling dimension is mm. JEDEC Designation: MS026 INCHES NOM MAX 0.055 0.063 0.004 0.006 0.002 0.011 0.354 0.366 0.28 0.280 0.354 0.366 0.28 0.280 0.020 0.024 0.24 0.030 4° 7.000° CS4294 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.20 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 0.40 0.50 BSC 0.60 0.45 0.60 0.00° ...
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Notes • ...
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