CS4294-JQ CIRRUS [Cirrus Logic], CS4294-JQ Datasheet - Page 33

• Manufacturer Part Number: CS4294-JQ
• Description: SoundFusion Audio/Docking Codec 97 (AMC 97)
• Manufacturer: CIRRUS [Cirrus Logic]

8. PIN DESCRIPTIONS
8.1 Digital I/O Pins
RESET# - AC ’97 Chip Reset, Input
SYNC - AC-link Serial Port Sync pulse, Input
DS326PP4
SDATA_OUT
This active low signal is the asynchronous Cold Reset input to the CS4294. The CS4294 must
be reset before it can enter normal operating mode. When the PR4 bit of register 26h is set, the
RESET# rising edge will be used as an AC ‘97 2.1 Warm Reset only, preserving register
values.
This signal is the serial port timing signal for the AC-link of the CS4294. Its period is the
reciprocal of the sample rate of the CS4294, 48 kHz. This signal is generated by the AC ’97
Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the
CS4294 is in a PR4 powerdown state and is configured as a primary codec. A series
terminating resistor of 47
signal.
SDATA_IN
XTL_OUT
BIT_CLK
RESET#
XTL_IN
DVdd1
DVdd2
DVss1
DVss2
GPIO3
SYNC
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TQFP
should be connected on this signal close to the device driving the
CS4294-XQ
36
35
34
33
32
31
30
29
28
27
26
25
AVdd3
ID0#
ALT_LINE_OUT_R
ALT_LINE_OUT_L
AVss2
AVdd2
LINE_OUT_R
LINE_OUT_L
ID1#
AFLT2
AFLT1
Vrefout
CS4294
33