CS4294-JQ CIRRUS [Cirrus Logic], CS4294-JQ Datasheet - Page 25

• Manufacturer Part Number: CS4294-JQ
• Description: SoundFusion Audio/Docking Codec 97 (AMC 97)
• Manufacturer: CIRRUS [Cirrus Logic]

6.1.19 Extended Codec ID (Index 3Ch)
ID[1:0]
Default
6.1.20 Extended Codec Status/Control (Index 3Eh)
PRH
PRG
PRD
PRC
PRB
PRA
EDAC2
EADC2
EDAC1
EADC1
EREF
GPIO
Default
DS326PP4
Mode
Mode
0
1
0
1
The Extended Codec ID is a read/write register. Writing any value to this location issues a reset to
the Extended Codec registers (Index 3Ch-56h). The primary Audio registers are not reset by a write
to this location.
NOTE: All GPIO registers (Index 46h-54h) are reset by any write to this location.
PR[A:D,G:H] are read/write bits that provide power management of the extended codec subsection.
All remaining bits are read/only status indicating the subsystems are ready for operation. After reset
or issuing a change to the MD[1:0] of AC Mode (Index 5Eh) register, the respective status bits for
that mode will be clear until the subsystem becomes ready.
ID1
ID1
PRH
D15
D15
Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the configuration
pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits in this reg-
ister.
Mode 0
Mode 1
Extended DAC2. When set powers down the Extended DAC2.
Extended ADC2. When set powers down the Extended ADC2.
Extended DAC2. When set powers down the Extended DAC1.
Extended ADC1. When set powers down the Extended ADC1.
Extended ADC/DAC Reference. When set powers down the extended ADC/DAC reference. The ex-
tended ADC/DAC and audio share a common reference. The reference will not power down unless PR3
of the Power Down Ctrl/Stat (Index 26h) register is also set.
GPIO. When set the GPIO pins are tri-state and powered down. Slot 12 is marked invalid if the AC-link
is active.
Extended DAC2. When set indicates the Extended DAC2 is ready.
Extended ADC2. When set indicates the Extended ADC2 is ready.
Extended DAC1. When set indicates the Extended DAC1 is ready.
Extended ADC1. When set indicates the Extended ADC1 is ready.
Extended ADC/DAC Reference. When set indicates the extended ADC/DAC reference is ready.
GPIO. When set the GPIO pins are ready. Slot 12 is marked valid.
Mode 0
Mode 1
ID0
ID0
PRG
PRG
D14
D14
D13
D13
x005h
x000h Where x is determined by the state of ID[1:0] input pins.
x0CFh
x047h Where x is determined by the state of ID[1:0] input pins.
D12
D12
PRD
D11
D11
PRC
PRC
D10
D10
PRB
PRB
D9
D9
PRA
PRA
D8
D8
EDAC2 EADC2
D7
D7
EADC2
D6
D6
D5
D5
D4
D4
EDAC1 EADC1 EREF
D3
D3
EADC1 EREF
D2
D2
CS4294
D1
D1
GPIO
GPIO
D0
D0
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