cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 46

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

Detailed Functional Description
3.4.4
3-20
Signal Level Adjust in the Digital Front End
Refer to
selected for BT.656 decoding and square-pixel rate decoding.
Two video standards, NTSC-J and PAL-N, require additional configuration to discern
between NTSC-M and PAL-BDGHI, respectively. For properly decoded black levels
with NTSC-J and PAL-N, the AFD_NTSC_SEL or AFD_PAL_SEL bit in the VIDEO
MODE CONTROL 1 register (0x400) must be set high to indicate to the decoder that
no pedestal is present on the input waveform.
The auto detection can also be manually overridden by programming the
VID_FMT_SEL bits in the VIDEO MODE CONTROL 1 register (0x400) to the
desired video standard to be decoded. Writing these VID_FMT_SEL bits to a forced
standard still enables automatic configuration of the registers to their respective
values but disables the function to automatically switch should a different video
standard be input. To completely disable the automatic register configuration, the
ACFG_DIS bit in Video Mode Control 1 (0x400) register should be set high.
When a video signal is first applied, the Digital Front End (DFE) block receives 8x
NTSC subcarrier, oversampled waveforms from the ADCs that have unknown
amplitude and offsets. The block then applies offset and gain to the input such that the
output of the DFE is aligned with expected levels for black and white. The DFE
controls the amplitude of the signal into the ADCs by implementing an AGC
algorithm to gain the signal based on the reference sync-tip amplitude. This AGC
algorithm coarsely controls the signal amplitude by adjusting the VGA gain in
discrete steps. Next, fine adjustment of the amplitude is accomplished by applying a
digital multiplier to the incoming signal.
Since some video equipment provides a less-than-standard sync tip, the decoder must
also adapt the gain accordingly. If the input signal contains white levels that exceed
the expected normal level, the luma processing block detects the occurrence of these
excursions past the normal peak white and updates the sync-tip height reference.
The DFE is also responsible for aligning the back porch to a standard level. It
measures the average level of the back porch level in the incoming signal, and then
adds an offset to the ADC data after it has passed through the gain stage.
For S-Video and component formats, the chroma and Pb/Pr ADC data must have their
own gain and offset applied. For these cases, the DFE uses the same gain value that
was determined from the luma channel for the chroma and Pb/Pr channels. However,
for the offset, different assumptions apply. In the case of S-Video, it assumes that the
chroma signal is balanced around the ADC’s mid-code value of 0x200. Any DC offset
from this ideal value should not matter once the AC waveform is passed through the
chroma demodulation stage. In the case of YPbPr video format, the offset is such that
the chroma value during the sync tip is clamped to the mid-code value of 0x200
(which is logically equivalent to U/V = 0).
The DFE is also partly responsible for determining when the input waveform is
clamped. The AFE attempts to clamp the sync tip to a level such that after passing
through the VGA stage, it is roughly the correct level. This requires the DFE to
provide both the clamping strobe during the sync pulse and a clamping level to the
AFE. The clamping level is provided through mapping based on the VGA setting.
These functions also serve to maximize the dynamic range of the ADC.
Alternatively, the automatic function of the VGA and AGC can be disabled by setting
the auto enable bits, VGA_AUTO_EN and AGC_AUTO_EN, in the DFE CONTROL
register (0x48B) low and manually setting the gain values through the VGA Gain
Tables 5-4
and 5-5, which show the register values when auto-detect mode is
Conexant
CX25840/1/2/3 Data Sheet
102284B
8/3/05