cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 74

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

Detailed Functional Description
3.6.8
3.6.9
3-48
VBI Controller
Clock Run-In Synchronization
Control of the VBI engine is through a state machine, which monitors the incoming
video and nonvideo data and initiates the VBI decoding process based on user defined
parameters of HDELAY, CRILK, FCBIT, and VBx_BYTE_COUNT. Other inputs to
the VBI state machine are from the Vertical Timing Generator (VTG), which outputs
both the vertical and horizontal reset. See
waveform consists of four major sections: hdelay, clock run-in, data run-in, (start/
frame code) and data payload (data capture).
Through the state machine, the VBI engine starts when either one of three conditions
occurs: vertical reset, a time-out of data run-in, or at the end of the previous line’s data
capture mode. When a horizontal reset occurs, the VBI engine goes into BREEZE
state for HDELAY clock cycles. Once HDELAY counter expires, it goes into a Clock
run-in state (CRILK) for the number of programmed clock run-in cycles to be
captured. It then switches to data run-in state (FCBIT). The VBI engine stays in this
state for FCBIT to capture the start bits, or the framing code in case of the Teletext
format. Then it switches to Data Capture mode to capture as many bits or bytes
specified by VBIx_CAP_COUNT. Note that the parameters described here can be
manually controlled through the custom modes, but they are configured automatically
in the autoconfiguration modes.
A discrete time oscillator determines the sample rate and positioning of the sample
points for each of the various VBI standards. A 14-bit counter, incremented by
VBIx_BITINC with each VBI clock, generates a pulse to mark each sample point.
This is used to measure sample periods as the state machine sequences through the
different stages of the VBI waveform.
During the clock run-in cycles, the logic performs three functions:
The slice level detector determines the “slice level” used to distinguish between a
logical 1 or 0 data sample. At the start of the clock run-in signal, an initial assumption
of 1.75 x the back-porch level is made for the initial slice level. This number is used as
a seed to the slice level calculation engine. Samples are taken at VBIx_SLCNT clocks
apart. Starting with the first zero crossing of the clock run-in, four samples are taken,
and the average of those samples is data and data run-in slice level.
During clock run-in, the logic detects the number of clock run-in cycles specified by
VBIx_CRILK. These clocks are detected in terms of rising edges on the input
waveform. At the end of this search, frequency lock is declared if the elapsed time lies
within the range specified by the VBIx_CKRGH and VBIx_CKRGL registers. These
registers specify time in terms of the VBI sample rate period. The DTO that is
controlled by the VBIx_BITINC parameter is used to count the sample periods. In
other words, the logic determines whether a defined number of clock run-in cycles
(VBIx_CRILK) elapsed in the expected time (VBIx_CKRGH and VBIx_CKRGL).
If frequency lock is determined, the sample period DTO is synchronized one more
time to the last negative edge of the clock run-in cycles. In the absence of frequency
lock, the state machine is reset to idle and waits for the next line.
1.
2.
3.
Measures the Slice Level
Synchronizes the slice timing to the clock run-in edges
Determines whether the clock run-in cycle has the expected frequency.
Conexant
Table 3-14
in
Section
3.6.3. The CC
CX25840/1/2/3 Data Sheet
102284B
8/3/05