cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 99

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

CX25840/1/2/3 Data Sheet
Figure 3-26. Output Signals Connection and Routing to Pins
102284B
8/3/05
GP Flop
GPO0
GPO1
GPO2
GPO3
Output Values
Register 126
Table 3-33. Alternate PRGM[0:7] Pin Functions
0 = Pin Dependant
1 = ACTIVE (Composite active or horizontal active indicator. See ACTFMT bit of OUT_CTRL1
register in video decoder core.
2 = VACTIVE (Vertical active indicator. Asserted during all vertical active lines
3 = CBFLAG (Cr/Cb indicator (0 = Cr, 1 = Cb) Cbflag is reset to cb at the beginning of each
line and toggles every pixel clock period.
4 = VID_DATA_EXT[0] (Extended Video Data. Least significant bits of internal 10-bit video
bus. When enabled, 10-bit video is possible.
5 = VID_DATA_EXT[1] (Extended Video Data. Least significant bits of internal 10-bit video
bus. When enabled, 10-bit video is possible.
6 = GPO[0] (Data from internal GPIO flops.
7 = GPO[1] (Data from internal GPIO flops.
8 = GPO[2] (Data from internal GPIO flops.
9 = GPO[3] (Data from internal GPIO flops.
A = IRQ_N/PRGM4 (Interrupt output: default active low polarity
B = AC_SYNC
C = AC_SDOUT
D = PLL_CLK
E = VRESET/HCTL/PRGM3 (vertical reset indicator)
F = RESERVED
Bit Location
0
1
2
3
Alternatively, the following functions in
Pin Configuration registers (0x11C to 0x122). The XXX_OUT_SEL field select
which internal signal is output on the PRGMx pin. The default output 0 value is
determined by the specific output pin.
Any signal shown in
Default unique to pin
ACTIVE
VACTIVE
CBFLAG
VID_DATA_EXT[0]
VID_DATA_EXT[1]
GPO[0]
GPO[1]
GPO[2]
GPO[3]
IRQ_N
AC_SYNC
AC_SDOUT
PLL_CLK
VRESET
RESERVED
Output Signals
Output Mux Value
Hex
)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Figure 3-26
Conexant
Pin #
)
17
23
22
21
18
10
8
9
7
4
46
)
)
)
)
CHIP_SEL/VIPCLK (GPO[0])
DVALID/PRGM0 (DVALID)
FIELD/PRGM1 (FIELD)
HRESET/PRGM2 (HRESET)
VRESET/HCTL/PRGM3 (VRESET)
IRQ_N/PRGM4 (IRQ_IN)
IR_TX/PRGM6 (IR_TX)
IR_RX/PRGM5 (GPO[2])
GPIO[0]/PRGM8 (GPO[0])
GPIO[1]/PRGM9 (GPO[1])
PLL_CLK_PRGM7 (PLL_CLK)
)
)
Name (Default)
can be routed to any pin.
Table 3-33
Pins/Output Mux
)
Register Bit
Enable
114
114
114
115
115
114
114
114
114
114
116
are available by programming the
2
6
7
0
1
3
5
4
0
1
2
.)
Output Mux Location
Detailed Functional Description
Register Bit
11D
11F
11F
120
120
11D
11E
11D
11D
11D
122
3:0
3:0
7:4
3:0
7:4
7:4
7:4
3:0
3:0
7:4
7:4, 2:0
102284_056
3-73