m5-128104-20vc Lattice Semiconductor Corp., m5-128104-20vc Datasheet - Page 14

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m5-128104-20vc

Manufacturer Part Number
m5-128104-20vc
Description
Fifth Generation Mach Architecture
Manufacturer
Lattice Semiconductor Corp.
Datasheet
BLOCK DIAGRAM — M5(LV)-128/XXX
14
CLK0
CLK1
CLK2
CLK3
I 0, 1
4
2
16
16
32
32
Block B/Macrocells 0-15
Block A/Macrocells 0-15
I 2, 3
2
2
Macrocells
Macrocells
I/O Cells
2
I/O Cells
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
16
16
16
64 PT
32
32
64 PT
16
16
16
32
32
Block B/Macrocells 0-15
Block A/Macrocells 0-15
64 x 73
S E G M E N T I N T E R C O N N E C T
64 x 73
2
2
7
7
Macrocells
Macrocells
I/O Cells
I/O Cells
Generator
Generator
Control
Control
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
16
16
16
16
64 PT
32
32
64 PT
2 PT OE
2 PT OE
7 PT
7 PT
64 x 73
64 x 73
SEGMENT 0
MACH 5 Family
Block Interconnect
7
7
Generator
Generator
Control
Control
2 PT OE
2 PT OE
7 PT
7 PT
SEGMENT 1
Block Interconnect
16
16
32
32
Block C/Macrocells 0-15
Block D/Macrocells 0-15
2
2
Macrocells
Macrocells
I/O Cells
I/O Cells
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
16
16
64 PT
32
32
64 PT
16
16
16
16
32
32
Block C/Macrocells 0-15
Block D/Macrocells 0-15
64 x 73
64 x 73
2
2
7
7
Macrocells
Macrocells
I/O Cells
I/O Cells
Generator
Generator
Control
Control
and Logic Allocator
and Logic Allocator
AND Logic Array
AND Logic Array
16
16
16
16
64 PT
64 PT
32
32
2 PT OE
2 PT OE
7 PT
7 PT
64 x 73
64 x 73
7
7
Generator
Generator
Control
Control
2 PT OE
2 PT OE
7 PT
7 PT
20446G-007

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