m5-128104-20vc Lattice Semiconductor Corp., m5-128104-20vc Datasheet - Page 9

• Manufacturer Part Number: m5-128104-20vc
• Description: Fifth Generation Mach Architecture
• Manufacturer: Lattice Semiconductor Corp.

MACH 5 TIMING MODEL
The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5
device, and at the same time, be easy to understand. This model accurately describes all
combinatorial and registered paths through the device, making a distinction between internal
feedback and external feedback. A signal uses internal feedback when it is fed back into the switch
matrix or block without having to go through the output buffer. The input register specifications
are also reported as internal feedback. When a signal is fed back into the switch matrix after having
gone through the output buffer, it is using external feedback.
The parameter, t
If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is
followed by an “i”. By adding t
For example, t
shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design
for a more detailed discussion about the timing parameters.
IN
CE
t
t
t
t
t
t
t
PD
SIR (S/A)
HIR (S/A)
SIL
HIL
SRR
CES
CEH
INPUT LATCH
INPUT REG/
BUF
= t
SR
, is defined as the time it takes to go through the output buffer to the I/O pad.
PDi
t
t
t
t
CO (S/A) i
PDILi
GOAi
SRi
+ t
Q
BUF
. A diagram representing the modularized MACH 5 timing model is
BUF
Figure 7. MACH 5 Timing Model
t
t
BLK
SEG
to this internal parameter, the external parameter is derived.
PIN CLK
MACH 5 Family
(External Feedback)
(Internal Feedback)
t
t
t
PL1
PL2
PL3
t
PT
CE
t
t
t
t
t
t
t
S (S/A)
H (S/A)
SAL
HAL
SRR
CES
CEH
COMB/DFF/
LATCH
SR
t
t
t
t
t
PDi
CO (S/A) i
PDLi
GOAi
SRi
Q
t
t
BUF
t
ER
EA
20446G-014
t
SLW
OUT
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