AM186EM-20KC/W AMD [Advanced Micro Devices], AM186EM-20KC/W Datasheet - Page 25

• Manufacturer Part Number: AM186EM-20KC/W
• Description: High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

PIN DESCRIPTIONS
Pins That Are Used by Emulators
The following pins are used by emulators: A19–A0,
AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the
Am186EM), CLKOUTA, R F S H 2/A D E N (on the
Am188EM), RD, S2–S0, S6/CLKDIV2, and UZI.
Emulators require that S6/CLKDIV2 and UZI be config-
ured in their normal functionality, that is as S6 and UZI.
If BHE/ADEN (on the 186) or RFSH2/ADEN (on the 188)
is held Low during the rising edge of RES, S6 and UZI are
configured in their normal functionality.
Pin Terminology
The following terms are used to describe the pins:
Input—An input-only pin.
Output—An output-only pin.
Input/Output—A pin that can be either input or output.
Synchronous—Synchronous inputs must meet setup
and hold times in relation to CLKOUTA. Synchronous
outputs are synchronous to CLKOUTA.
A s y n c h r o n o u s — I n p u t s o r o u t p u t s t h a t a r e
asynchronous to CLKOUTA.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O ad-
dresses to the system one-half of a CLKOUTA period
earlier than the multiplexed address and data bus
(AD15–AD0 on the 186 or AO15–AO8 and AD7–AD0
on the 188). During a bus hold or reset condition, the
address bus is in a high-impedance state.
AD7
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. This bus
supplies the low-order 8 bits of an address to the sys-
tem during the first period of a bus cycle (t
plies data to the system during the remaining periods of
that cycle (t
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WLB is negated, these pins are three-stated during t
t
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
3
, and t
–
AD0
4
.
2
, t
3
, and t
4
).
Am186/188EM and Am186/188EMLV Microcontrollers
1
), and it sup-
P R E L I M I N A R Y
2
,
During a power-on reset, the address and data bus
pins (AD15–AD0 for the 186, AO15–AO8 and AD7–
AD0 for the 188) can also be used to load system con-
figuration information into the internal reset configura-
tion register.
AD15
AO15
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
Address-Only Bus (output, three-state,
synchronous, level-sensitive)
AD15–AD8—On the Am186EM microcontroller, these
time-multiplexed pins supply memory or I/O addresses
and data to the system. This bus can supply an ad-
dress to the system during the first period of a bus cycle
(t
periods of that cycle (t
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is negated, these pins are three-stated during t
and t
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the 186, AO15–AO8 and AD7–
AD0 for the 188) can also be used to load system con-
figuration information into the internal reset configura-
tion register.
AO15–AO8—On the Am188EM microcontroller, the
address-only bus (AO15–AO8) contains valid high-
order address bits from bus cycles t
are floated during a bus hold or reset.
On the Am188EM microcontroller, AO15–AO8 com-
bine with AD7–AD0 to form a complete multiplexed ad-
dress bus while AD7–AD0 is the 8-bit data bus.
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address ap-
pears on the address and data bus (AD15–AD0 for the
186 or AO15–AO8 and AD7–AD0 for the 188). The ad-
dress is guaranteed valid on the trailing edge of ALE.
This pin is three-stated during ONCE mode. This pin is
not three-stated during a bus hold or reset.
ARDY
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin indicates to the microcontroller that the ad-
dressed memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that
is asynchronous to CLKOUTA and is active High. The
1
). It supplies data to the system during the remaining
4.
–
–
AD8 (Am186EM Microcontroller)
AO8 (Am188EM Microcontroller)
2
, t
3
, and t
4
).
1
–t
4
. These outputs
2
, t
25
3
,