AM186EM-20KC/W AMD [Advanced Micro Devices], AM186EM-20KC/W Datasheet - Page 61

• Manufacturer Part Number: AM186EM-20KC/W
• Description: High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

Alphabetical Key to Switching Parameter Symbols
Note:
The following parameters are not defined or used as this time: 41, 56, 60, 73, 74, 76.
Parameter
Symbol
t
t
t
t
t
t
t
t
ARYCHL
t
t
t
t
ARYLCL
CH1CH2
t
t
t
t
ARYCH
t
t
t
t
t
CHCSV
CHCSX
t
t
t
CHRFD
t
CL2CL1
t
t
t
CHCTV
t
t
t
CLARX
t
t
t
t
CLCSV
CLDOX
t
t
t
CICOA
CICOB
t
t
CLCLX
CLCSL
t
AVCH
AVWL
CHAV
CHCK
CHCV
CHCZ
CHDX
CHSV
AVRL
CHCL
CHLH
CKHL
CKLH
CLAV
CLAX
CLCH
CLCK
CLDV
AVBL
AVLL
AZRL
CHLL
CLAZ
CLCL
CKIN
No.
49
51
52
87
14
12
66
65
24
45
68
38
44
67
18
22
64
63
11
79
69
70
39
36
40
46
50
15
43
37
42
80
81
16
30
8
9
3
5
6
7
ARDY Resolution Transition Setup Time
ARDY Inactive Holding Time
ARDY Setup Time
A Address Valid to WHB, WLB Low
AD Address Valid to Clock High
AD Address Valid to ALE Low
A Address Valid to RD Low
A Address Valid to WR Low
AD Address Float to RD Active
CLKOUTA Rise Time
CLKOUTA High to A Address Valid
X1 High Time
CLKOUTA High Time
CLKOUTA High to LCS/UCS Valid
MCS/PCS Inactive Delay
Control Active Delay 2
Command Lines Valid Delay (after Float)
Command Lines Float Delay
Status Hold Time
ALE Active Delay
ALE Inactive Delay
CLKOUTA High to RFSH valid
Status Active Delay
X1 to CLKOUTA Skew
X1 to CLKOUTB Skew
X1 Fall Time
X1 Period
X1 Rise Time
CLKOUTA Fall Time
ARDY Active Hold Time
AD Address Valid Delay
Address Hold
AD Address Float Delay
CLKOUTA Low Time
X1 Low Time
CLKOUTA Period
LCS Inactive Delay
LCS Active Delay
MCS/PCS Active Delay
Data Hold Time
Data Valid Delay
Am186/188EM and Am186/188EMLV Microcontrollers
Description
P R E L I M I N A R Y
Parameter
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
COAOB
t
t
WHDEX
t
t
CVDEX
CXCSX
t
t
t
t
t
t
t
t
t
t
CLHAV
t
t
t
CLSRY
CLTMV
CVCTV
CVCTX
t
t
t
t
t
t
SRYCL
t
INVCH
t
t
t
WHDX
WLWH
INVCL
RESIN
WHLH
CLDX
CLRH
CLSH
DVSH
LOCK
RFCY
RHAV
RHDX
RHLH
RLRH
SHDX
CLEV
CLRF
CLRL
CLSL
DVCL
DXDL
HVCL
LCRF
LHAV
SLDV
LHLL
LLAX
LRLL
No.
71
62
82
27
25
72
48
55
83
20
31
21
17
75
19
58
53
54
86
23
10
13
61
84
57
85
29
59
28
26
77
78
47
35
34
33
32
2
4
1
Data in Hold
CLKOUTA Low to SDEN Valid
HLDA Valid Delay
CLKOUTA High to RFSH Invalid
RD Inactive Delay
RD Active Delay
Status Inactive Delay
CLKOUTA Low to SCLK Low
SRDY Transition Hold Time
Timer Output Delay
CLKOUTA to CLKOUTB Skew
Control Active Delay 1
Control Inactive Delay
DEN Inactive Delay
MCS/PCS Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
DEN Inactive to DT/R Low
HOLD Setup
Peripheral Setup Time
DRQ Setup Time
LCS Inactive to RFSH Active Delay
ALE High to Address Valid
ALE Width
AD Address Hold from ALE Inactive
Maximum PLL Lock Time
LCS Precharge Pulse Width
RES Setup Time
RFSH Cycle Time
RD Inactive to AD Address Active
RD High to Data Hold on AD Bus
RD Inactive to ALE High
RD Pulse Width
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
SRDY Transition Setup Time
WR Inactive to DEN Inactive
Data Hold after WR
WR Inactive to ALE High
WR Pulse Width
Description
61