C505-2RM SIEMENS [Siemens Semiconductor Group], C505-2RM Datasheet - Page 42

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C505-2RM

Manufacturer Part Number
C505-2RM
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
10-Bit A/D Converter (C505A and C505CA only)
The C505 includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input
channels. It operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The A/D converter
provides the following features:
The 10-bit ADC uses two clock signals for operation : the conversion clock
input clock
XTAL pins. The input clock
frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.
Figure 19
10-Bit A/D Converter Clock Selection
Semiconductor Group
– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors
MCU System Clock
Rate (
12 MHz
16 MHz
20 MHz
2 MHz
6 MHz
8 MHz
f
IN
(=1/
f
Condition:
OSC
f
OSC
t
IN
)
). f
ADC
f
ADC max
Clock Prescaler
f
IN
ADCL1
is derived from the C505 system clock
32
16
8
4
f
[MHz]
12
16
20
is equal to
IN
2
6
8
< 2 MHz
MUX
f
ADCL0
OSC
Prescaler
Ratio
f
Conversion Clock
IN
4
4
4
8
8
16
= f
The conversion
42
OSC
Input Clock
=
CLP
f
[MHz]
0.5
1.5
2
1.5
2
1.25
1
ADC
f
ADC
f
f
IN
ADC
clock is limited to a maximum
1
ADCL1
0
0
0
0
0
f
OSC
Converter
A / D
MCS03635
which is applied at the
f
ADC
C505A / C505CA
(=1/
C505 / C505C
ADCL0
0
0
0
1
1
0
t
ADC
1997-12-01
) and the

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