LTAEY LINEAR [Linear Integrated Systems], LTAEY Datasheet - Page 6

• Manufacturer Part Number: LTAEY
• Description: Differential Input 16-Bit No Latency DS ADC
• Manufacturer: LINEAR [Linear Integrated Systems]

PI FU CTIO S
LTC2433-1
V
a 10 F tantalum capacitor in parallel with 0.1 F ceramic
capacitor as close to the part as possible.
REF
The voltage on these pins can have any value between GND
and V
maintained more positive than the reference negative
input, REF
IN
voltage on these analog inputs can have any value between
GND and V
input range (V
to 0.5 • (V
produces unique overrange and underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
6
CC
+
U
(Pin 4), IN
(Pin 1): Positive Supply Voltage. Bypass to GND with
+
(Pin 2), REF
CC
as long as the reference positive input, REF
U
–
REF
CC
, by at least 0.1V.
. Within these limits the converter bipolar
IN
). Outside this input range the converter
–
= IN
(Pin 5): Differential Analog Input. The
–
U
(Pin 3): Differential Reference Input.
+
– IN
–
) extends from – 0.5 • (V
REF
+
, is
)
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
controls the ADC’s notch frequencies and conversion
time. When the F
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When F
clock signal with a frequency f
signal as its system clock and the digital filter has 87dB
minimum rejection in the range f
110dB minimum rejection at f
O
(Pin 10): Frequency Control Pin. Digital input that
O
pin is connected to GND (F
EOSC
EOSC
O
is driven by an external
, the converter uses this
CC
EOSC
/2560 4%.
) the SDO pin is in a
/2560 14% and
O
= 0V), the
24331fa