LTC1290BI LINER [Linear Technology], LTC1290BI Datasheet
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LTC1290BI
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LTC1290BI Summary of contents
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FEATURE S Software Programmable Features – Unipolar/Bipolar Conversion – Four Differential/Eight Single-Ended Inputs – MSB- or LSB-First Data Sequence – Variable Data Word Length – Power Shutdown Built-In Sample-and-Hold Single Supply Operation Direct Four-Wire Interface to Most ...
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... (Notes 1, 2) – ........................ 12V Operating Temperature Range LTC1290BC, LTC1290CC, LTC1290DC .... LTC1290BI, LTC1290CI, LTC1290DI .... – – ) – 0. 0.3V LTC1290BM, LTC1290CM, CC LTC1290DM....................................... – 125 C + 0.3V Storage Temperature Range ................ – 150 C CC Lead Temperature (Soldering, 10 sec.)................ 300 C ...
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... (Note (Note 6) CC (Note 9) See Operating Sequence See Operating Sequence See Operating Sequence (Note 6) See Test Circuits LTC1290BC, LTC1290CC LTC1290DC, LTC1290BI LTC1290CI, LTC1290DI LTC1290BM, LTC1290CM LTC1290DM See Test Circuits Enabled See Test Circuits (Note (Note 6) ...
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... CC 1290 • TPC01 4 HARA TER STICS C CONDITIONS OUT CC CS High CS High LTC1290BC, LTC1290CC Power Shutdown LTC1290DC, LTC1290BI ACLK Off LTC1290CI, LTC1290DI LTC1290BM, LTC1290CM LTC1290DM REF CS High – below V or one diode drop above levels (4.5V), as high level reference or analog inputs (5V) can cause ...
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W U TYPICAL PERFOR A Change in Linearity vs Reference Voltage 1. 1.00 0.75 0.50 0. REFERENCE VOLTAGE, V (V) REF 1290 • TPC04 Change in Linearity Error vs Temperature ...
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LTC1290 W U TYPICAL PERFOR A Sample-and-Hold Acquisition Time vs Source Resistance 100 REF INPUT STEP R + SOURCE + – 1 ...
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CTIO S D (Pin 17): Digital Data Input. The A/D configuration IN word is shifted into this input after CS is recognized. SCLK (Pin 18): Shift Clock. This clock synchronizes the serial data transfer. BLOCK ...
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LTC1290 TEST CIRCUITS D ACLK CS D OUT WAVEFORM 1 (SEE NOTE 1) D OUT WAVEFORM 2 (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY ...
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PPLICATI FOR ATIO The LTC1290 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, full duplex ...
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LTC1290 PPLICATI S I FOR ATIO MUX Address The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between ...
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PPLICATI S I FOR ATIO Unipolar/Bipolar (UNI) The fifth input bit (UNI) determines whether the conver- sion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the ...
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LTC1290 PPLICATI S I FOR ATIO MSB-First/LSB-First Format (MSBF) The output data of the LTC1290 is programmed for MSB- first or LSB-first sequence using the MSBF bit. For MSB first output data the input word clocked ...
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PPLICATI S I FOR ATIO 8-Bit Word Length CS SCLK 1 (SB) D OUT B11 B10 MSB-FIRST D OUT B0 B1 LSB-FIRST 12-Bit Word Length CS 1 SCLK (SB) D OUT B11 B10 MSB-FIRST D OUT ...
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LTC1290 PPLICATI S I FOR ATIO SHIFT MUX ADDRESS SAMPLE ANALOG IN CS SCLK B11 B10 OUT SHIFT MUX ADDRESS SAMPLE ANALOG IN CS SCLK ...
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PPLICATI S I FOR ATIO A Table 2. Microprocessors with Hardware Serial Interfaces Compatible with the LTC1290** PART NUMBER TYPE OF INTERFACE Motorola MC6805S2, S3 SPI MC68HC11 SPI MC68HC05 SPI RCA CDP68HC05 SPI Hitachi HD6305 SCI Synchronous ...
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LTC1290 PPLICATI S I FOR ATIO Hardware and Software Interface to Motorola MC68HC05C4 Processor LTC1290 CS SCLK • ANALOG • INPUTS D IN • • D OUT D from LTC1290 Stored in MC68HC05C4 RAM OUT MSB* ...
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PPLICATI FOR ATIO 8051 Code MNEMONIC COMMENTS MOV P1,#02H Bit 1 Port 1 Set as Input CLR P1.3 SCLK Goes Low SETB P1.4 CS Goes High CONT MOV A,#0EH D Word for LTC1290 IN ...
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LTC1290 PPLICATI S I FOR ATIO TANTALUM ANALOG GROUND PLANE Figure 6. Example Ground Plane for the LTC1290 Figure 6 shows an example of an ideal ground plane design ...
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PPLICATI S I FOR ATIO “+” INPUT R + SOURCE 4TH SCLK C1 “–” INPUT R – LAST SCLK SOURCE V – Figure 9. Analog Input Equivalent Circuit “+” Input Settling ...
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LTC1290 PPLICATI S I FOR ATIO clock rates (ACLK = 4MHz and SCLK = 2MHz). Figures 11 and 12 show examples of adequate and poor op amp settling. HORIZONTAL: 500ns/DIV Figure 11. Adequate Settling of Op ...
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PPLICATI S I FOR ATIO Differential Inputs With differential inputs or when the COM pin is not tied to ground, the A/D no longer converts just a single voltage but rather the difference between two voltages. ...
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LTC1290 PPLICATI FOR ATIO 6. Reduced Reference Operation The effective resolution of the LTC1290 can be increased by reducing the input span of the converter. The LTC1290 exhibits good linearity and gain over a ...
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PPLICATI FOR ATIO f = 1kHz SAMPLE SNR = 73.25dB –20 –40 –60 –80 –100 –120 –140 FREQUENCY (kHz) Figure 17a. LTC1290 FFT Plot f 12 ...
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LTC1290 PPLICATI S I FOR ATIO larger current limiting resistors. Use 1N4148 diode clamps – from the MUX inputs to V and V if the value of the series CC resistor will not allow the maximum ...
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U O TYPICAL A PPLICATI ACLK/ SCLK TM SNEAK-A-BIT The LTC1290’s unique ability to software select the polar- ity of the differential inputs and the output word length is used to achieve one more bit of resolution. Using the circuit ...
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LTC1290 O U TYPICAL A PPLICATI SNEAK-A-BIT Code D from LTC1290 in MC68HC05C4 RAM OUT Sign LOCATION $77 B12 B11 B10 LSB LOCATION $ Filled with 0s D Words for LTC1290 IN ...
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O U TYPICAL A PPLICATI Power Shutdown For battery-powered applications it is desirable to keep power dissipation at a minimum. The LTC1290 can be powered down when not in use reducing the supply current from a nominal value of 5mA ...
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LTC1290 PACKAGE DESCRIPTIO 0.300 BSC CORNER LEADS OPTION (0.762 BSC) (4 PLCS) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD 0.008 – 0.018 OPTION 0 – 15 (0.203 – 0.457) 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION NOTE: ...