LTC1290BI LINER [Linear Technology], LTC1290BI Datasheet - Page 15

• Manufacturer Part Number: LTC1290BI
• Description: Single Chip 12-Bit Data Acquisition System
• Manufacturer: LINER [Linear Technology]

Table 2. Microprocessors with Hardware Serial Interfaces
Compatible with the LTC1290**
Motorola
RCA
Hitachi
National Semiconductor
Texas Instruments
** Contact factory for interface information for processors not on this list
A
*Requires external hardware
PPLICATI
ANALOG
INPUTS
Hardware and Software Interface to COP402 Processor
PART NUMBER
MC6805S2, S3
MC68HC11
MC68HC05
CDP68HC05
HD6305
HD6301
HD63701
HD6303
HD64180
COP400 Family
COP800 Family
NS8050U
HPC16000 Family
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
TMS370C050
D
LOCATION $13
LOCATION $14
LOCATION $15
†
•
•
•
•
OUT
B11 IS MSB IN UNIPOLAR OR SIGN BIT IN BIPOLAR
O
from LTC1290 Stored in COP402 RAM
LTC1290
U
S
D OUT
MSB
SCLK
B11
D IN
B7
B3
CS
†
I FOR ATIO
U
B10
B6
B2
TYPE OF INTERFACE
SPI
SPI
SPI
SPI
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
MICROWIRE
MICROWIRE/PLUS
MICROWIRE/PLUS
MICROWIRE/PLUS
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI
B5
B1
B9
W
LSB
B8
SK
SO
B4
B0
GO
SI
COP402
FIRST 4 BITS
SECOND 4 BITS
THIRD 4 BITS
TM
LTC1290 • AI08
TM
U
National MICROWIRE (COP402)
The COP402 transfers data MSB first and in 4-bit incre-
ments (nibbles). This is easily accommodated by setting
the LTC1290 to MSB-first format and 12-bit word length.
The data output word is then received by the COP402 in
three 4-bit blocks.
COP402 Code
LOOP
Motorola SPI (MC68HC05C4)
The MC68HC05C4 transfers data MSB first and in 8-bit
increments. Programming the LTC1290 for MSB-first
format and 16-bit word length allows the 12-bit data
output to be received by the MPU as two 8-bit bytes with
the final four unused bits filled with zeros by the LTC1290.
MICROWIRE and MICROWIRE PLUS are trademarks of National Semiconductor Corp
MNEMONIC
CLRA
LBI
STII 8
STII E
STII 0
LEI
SC
LDD 1,0
OGI 0
XAS
LDD 1,1
NOP
XAS
XIS
LDD 1,2
XAS
XIS
RC
CLRA
XAS
OGI 1
XIS
LBI
1,0
C
0
0
0
1,3
Must be First Instruction
BR = 1BD = 0 Initialize B Reg.
First D
Second D
Null Data in $12, B = $13
Set EN to (1100) BIN
Carry Set
Load First D
Go (CS) Cleared
ACC to Shift Reg. Begin Shift
Load Next D
Timing
Next Nibble, Shift Continues
First Nibble D
Put Null Data in ACC
Shift Continues, D
Next Nibble D
Clear Carry
Clear ACC
Third Nibble D
Go (CS) Set
Third Nibble D
Set B Reg. For Next Loop
IN
Nibble in $10
COMMENTS
IN
Nibble in $11
IN
IN
OUT
OUT
OUT
OUT
Nibble In ACC
Nibble in ACC
to $13
to $14
OUT
to ACC
to $15
LTC1290
to ACC
15