LTC1746 LINER [Linear Technology], LTC1746 Datasheet - Page 11

• Manufacturer Part Number: LTC1746
• Description: Low Power,14-Bit, 25Msps ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
CONVERTER OPERATION
As shown in Figure 1, the LTC1746 is a CMOS pipelined
multistep converter. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later, see the Timing Diagram section.
The analog input is differential for improved common
mode noise immunity and to maximize the input range.
Additionally, the differential input drive will reduce even
order harmonics of the sample-and-hold circuit. The en-
code input is also differential for improved common mode
noise immunity.
The LTC1746 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For
SENSE
4.7 F
A
A
V
IN
IN
CM
+
–
INPUT
REFERENCE
S/H
SELECT
RANGE
2.35V
REF
BUF
U
U
FIRST STAGE
ADC STAGE
PIPELINED
5-BIT
W
DIFF
AMP
REF
0.1 F
REFLB
1 F
REFERENCES TO ADC
Figure 1. Functional Block Diagram
INTERNAL
REFHA
U
4.7 F
SECOND STAGE
ADC STAGE
PIPELINED
4-BIT
REFLA
1 F
0.1 F
REFHB
CLOCK SIGNALS
brevity, the text will refer to ENC greater than ENC as ENC
high and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
DIFFERENTIAL
LOW JITTER
INTERNAL
DRIVER
CLOCK
INPUT
ENC
ENC
THIRD STAGE
ADC STAGE
PIPELINED
4-BIT
MSBINV
CONTROL
LOGIC
SHIFT REGISTER AND CORRECTION
OE
FOURTH STAGE
FLASH
4-BIT
ADC
DRIVERS
OUTPUT
LTC1746
OGND
11
OV
0.5V TO
5V
OF
D13
D0
CLKOUT
•
•
•
1746f
1746 F01
DD